Stamper; Anthony Kendall

Patent Applications and Registrations

Patent applications and USPTO patent grants for Stamper; Anthony Kendall.The latest application filed is for "gallium nitride (gan) power amplifiers (pa) with angled electrodes and 100 cmos and method for producing the same".

Company Profile

7.63.56

Stamper; Anthony Kendall - Burlington VT
Stamper; Anthony Kendall - Essex Junction VT
Stamper; Anthony Kendall - Williston VT
- Williston VT US
Stamper, Anthony Kendall - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Lamb acoustic wave resonator and filter with self-aligned cavity via Grant 10,784,833 - Campanella Pineda , et al. Sept	2020-09-22
Gallium nitride (GaN) power amplifiers (PA) with angled electrodes and 100 CMOS and method for producing the same Grant 10,469,041 - Stamper , et al. No	2019-11-05
Gallium Nitride (gan) Power Amplifiers (pa) With Angled Electrodes And 100 Cmos And Method For Producing The Same App 20190238105 - STAMPER; Anthony Kendall ; et al.	2019-08-01
Monolithic integration of MEMS and IC devices Grant 10,189,705 - Campanella Pineda , et al. Ja	2019-01-29
Lamb Acoustic Wave Resonator And Filter With Self-aligned Cavity Via App 20180287587 - CAMPANELLA PINEDA; Humberto ; et al.	2018-10-04
Curvilinear wiring structure to reduce areas of high field density in an integrated circuit Grant 9,275,951 - Anderson , et al. March 1, 2	2016-03-01
Methods for controlling wafer curvature Grant 08918988 -	2014-12-30
Methods for controlling wafer curvature Grant 8,918,988 - Fayaz , et al. December 30, 2	2014-12-30
Tapered Via And Mim Capacitor App 20140151851 - DUNN; JAMES STUART ; et al.	2014-06-05
Tapered via and MIM capacitor Grant 8,649,153 - Dunn , et al. February 11, 2	2014-02-11
Through substrate via including variable sidewall profile Grant 8,643,190 - Cooney, III , et al. February 4, 2	2014-02-04
Curvilinear Wiring Structure To Reduce Areas Of High Field Density In An Integrated Circuit App 20130307158 - Anderson; Felix Patrick ; et al.	2013-11-21
Curvilinear wiring structure to reduce areas of high field density in an integrated circuit Grant 8,530,970 - Anderson , et al. September 10, 2	2013-09-10
Through wafer vias and method of making same Grant 8,518,787 - Ding , et al. August 27, 2	2013-08-27
Double-sided integrated circuit chips Grant 8,471,306 - Bernstein , et al. June 25, 2	2013-06-25
Double-sided integrated circuit chips Grant 8,421,126 - Bernstein , et al. April 16, 2	2013-04-16
Through wafer vias and method of making same Grant 8,384,224 - Ding , et al. February 26, 2	2013-02-26
Methods And Structures For Controlling Wafer Curvature App 20120329265 - Fayaz; Mohammed Fazil ; et al.	2012-12-27
Through Wafer Vias And Method Of Making Same App 20120329219 - Ding; Hanyi ; et al.	2012-12-27
Through wafer vias and method of making same Grant 8,299,566 - Ding , et al. October 30, 2	2012-10-30
Methods and structures for controlling wafer curvature Grant 8,299,615 - Fayaz , et al. October 30, 2	2012-10-30
Fuse and pad stress relief Grant 8,137,791 - Anderson , et al. March 20, 2	2012-03-20
Double-sided Integrated Circuit Chips App 20110302542 - Bernstein; Kerry ; et al.	2011-12-08
By-product collecting processes for cleaning processes Grant 8,052,799 - Cooney, III , et al. November 8, 2	2011-11-08
Through wafer via and method of making same Grant 8,035,198 - Ding , et al. October 11, 2	2011-10-11
Double-sided Integrated Circuit Chips App 20110241082 - Bernstein; Kerry ; et al.	2011-10-06
Interconnect layers without electromigration Grant 8,026,606 - Luce , et al. September 27, 2	2011-09-27
Double-sided integrated circuit chips Grant 8,013,342 - Bernstein , et al. September 6, 2	2011-09-06
Double-sided integrated circuit chips Grant 7,989,312 - Bernstein , et al. August 2, 2	2011-08-02
Dual wired integrated circuit chips Grant 7,960,245 - Bernstein , et al. June 14, 2	2011-06-14
Through Substrate Annular Via Including Plug Filler App 20110129996 - Lindgren; Peter James ; et al.	2011-06-02
Dual wired integrated circuit chips Grant 7,939,914 - Bernstein , et al. May 10, 2	2011-05-10
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material Grant 7,915,134 - Chinthakindi , et al. March 29, 2	2011-03-29
Through Substrate Via Including Variable Sidewall Profile App 20110068477 - Cooney, III; Edward Crandal ; et al.	2011-03-24
Methods And Structures For Controlling Wafer Curvature App 20110049723 - Fayaz; Mohammed Fazil ; et al.	2011-03-03
Through substrate annular via including plug filler Grant 7,898,063 - Lindgren , et al. March 1, 2	2011-03-01
Through substrate via including variable sidewall profile Grant 7,863,180 - Cooney, III , et al. January 4, 2	2011-01-04
Dual-sided chip attached modules Grant 7,863,734 - Bernstein , et al. January 4, 2	2011-01-04
Structures including integrated circuits for reducing electromigration effect Grant 7,861,204 - Stamper , et al. December 28, 2	2010-12-28
Low resistance and inductance backside through vias and methods of fabricating same Grant 7,851,923 - Erturk , et al. December 14, 2	2010-12-14
Post last wiring level inductor using patterned plate process Grant 7,763,954 - Chinthakindi , et al. July 27, 2	2010-07-27
Post last wiring level inductor using patterned plate process Grant 7,741,698 - Chinthakindi , et al. June 22, 2	2010-06-22
Post last wiring level inductor using patterned plate process Grant 7,732,295 - Chinthakindi , et al. June 8, 2	2010-06-08
Post last wiring level inductor using patterned plate process Grant 7,732,294 - Chinthakindi , et al. June 8, 2	2010-06-08
Shallow and deep trench isolation structures in semiconductor integrated circuits Grant 7,723,178 - Adkisson , et al. May 25, 2	2010-05-25
Double-sided integrated circuit chips Grant 7,670,927 - Bernstein , et al. March 2, 2	2010-03-02
Double-sided Integrated Circuit Chips App 20100044759 - Bernstein; Kerry ; et al.	2010-02-25
Integration circuits for reducing electromigration effect Grant 7,667,328 - Stamper , et al. February 23, 2	2010-02-23
Through Wafer Via And Method Of Making Same App 20100032808 - Ding; Hanyi ; et al.	2010-02-11
Through Wafer Vias And Method Of Making Same App 20100032811 - Ding; Hanyi ; et al.	2010-02-11
Through Wafer Vias And Method Of Making Same App 20100032810 - Ding; Hanyi ; et al.	2010-02-11
Shallow And Deep Trench Isolation Structures In Semiconductor Integrated Circuits App 20100015765 - Adkisson; James William ; et al.	2010-01-21
Interconnect Layers Without Electromigration App 20090309223 - Luce; Stephen Ellinwood ; et al.	2009-12-17
Through Substrate Via Including Variable Sidewall Profile App 20090278237 - Cooney, III; Edward Crandal ; et al.	2009-11-12
Dielectric layers for metal lines in semiconductor chips Grant 7,598,166 - He , et al. October 6, 2	2009-10-06
Interconnect layers without electromigration Grant 7,585,758 - Luce , et al. September 8, 2	2009-09-08
Through Substrate Annular Via Including Plug Filler App 20090206488 - Lindgren; Peter James ; et al.	2009-08-20
Post last wiring level inductor using patterned plate process Grant 7,573,117 - Chinthakindi , et al. August 11, 2	2009-08-11
Low Resistance And Inductance Backside Through Vias And Methods Of Fabricating Same App 20090184423 - Erturk; Mete ; et al.	2009-07-23
Low resistance and inductance backside through vias and methods of fabricating same Grant 7,563,714 - Erturk , et al. July 21, 2	2009-07-21
Design Structures Including Integrated Circuits For Reducing Electromigration Effect App 20090164964 - Stamper; Anthony Kendall ; et al.	2009-06-25
Fuse And Pad Stress Relief App 20090155541 - Anderson; Felix Patrick ; et al.	2009-06-18
Reduced Electromigration And Stressed Induced Migration Of Cu Wires By Surface Coating App 20090142924 - Hu; Chao-Kun ; et al.	2009-06-04
Annular damascene vertical natural capacitor Grant 7,538,006 - Anderson , et al. May 26, 2	2009-05-26
Double-sided Integrated Circuit Chips App 20090121260 - Bernstein; Kerry ; et al.	2009-05-14
Dual Wired Integrated Circuit Chips App 20090121287 - Bernstein; Kerry ; et al.	2009-05-14
Method for reducing foreign material concentrations in etch chambers Grant 7,517,802 - Cooney, III , et al. April 14, 2	2009-04-14
Dual-sided Chip Attached Modules App 20090065925 - Bernstein; Kerry ; et al.	2009-03-12
Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material App 20090004809 - Chinthakindi; Anil Kumar ; et al.	2009-01-01
Dual-sided chip attached modules Grant 7,462,509 - Bernstein , et al. December 9, 2	2008-12-09
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080293210 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080290458 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080293233 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080277759 - Chinthakindi; Anil Kumar ; et al.	2008-11-13
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080272458 - Chinthakindi; Anil Kumar ; et al.	2008-11-06
Dual Wired Integrated Circuit Chips App 20080213948 - Bernstein; Kerry ; et al.	2008-09-04
Integration Circuits For Reducing Electromigration Effect App 20080203495 - Stamper; Anthony Kendall ; et al.	2008-08-28
Removal Of Etching Process Residual In Semiconductor Fabrication App 20080174015 - Herrin; Russell Thomas ; et al.	2008-07-24
Dual Wired Integrated Circuit Chips App 20080128812 - Bernstein; Kerry ; et al.	2008-06-05
Dual wired integrated circuit chips Grant 7,381,627 - Bernstein , et al. June 3, 2	2008-06-03
Interconnect Layers Without Electromigration App 20080105977 - Luce; Stephen Ellinwood ; et al.	2008-05-08
By-product Collecting Processes For Cleaning Processes App 20080093212 - Cooney; Edward Crandal ; et al.	2008-04-24
Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric Grant 7,361,950 - Chinthakindi , et al. April 22, 2	2008-04-22
Dielectric layers for metal lines in semiconductor chips App 20080061403 - He; Zhong-Xiang ; et al.	2008-03-13
Double-sided Integrated Circuit Chips App 20070267723 - Bernstein; Kerry ; et al.	2007-11-22
Dual-sided Chip Attached Modules App 20070267746 - Bernstein; Kerry ; et al.	2007-11-22
Dual Wired Integrated Circuit Chips App 20070267698 - Bernstein; Kerry ; et al.	2007-11-22
Dual wired integrated circuit chips Grant 7,285,477 - Bernstein , et al. October 23, 2	2007-10-23
Low Resistance And Inductance Backside Through Vias And Methods Of Fabricating Same App 20070190692 - Erturk; Mete ; et al.	2007-08-16
Method For Reducing Foreign Material Concentrations In Etch Chambers App 20070066067 - Cooney; Edward Crandal III ; et al.	2007-03-22
Method for reducing foreign material concentrations in etch chambers Grant 7,192,874 - Cooney, III , et al. March 20, 2	2007-03-20
Integration Of A Mim Capacitor Over A Metal Gate Or Silicide With High-k Dielectric Materials App 20070057343 - Chinthakindi; Anil Kumar ; et al.	2007-03-15
Post Last Wiring Level Inductor Using Patterned Plate Process App 20070026659 - Chinthakindi; Anil Kumar ; et al.	2007-02-01
Reduced electromigration and stressed induced migration of copper wires by surface coating App 20050266673 - Hu, Chao-Kun ; et al.	2005-12-01
Electrically tunable on-chip resistor Grant 6,960,744 - Adkisson , et al. November 1, 2	2005-11-01
Method For Manufacturing Self-compensating Resistors Within An Integrated Circuit App 20050227449 - Murphy, William Joseph ; et al.	2005-10-13
Specially shaped contact via and integrated circuit therewith Grant 6,924,555 - Cronin , et al. August 2, 2	2005-08-02
Electrically Tunable On-chip Resistor App 20050030149 - Adkisson, James W. ; et al.	2005-02-10
Method For Reducing Foreign Material Concentrations In Etch Chambers App 20050014369 - Cooney, III, Edward Crandal ; et al.	2005-01-20
One-mask metal-insulator-metal capacitor and method for forming same Grant 6,750,114 - Adler , et al. June 15, 2	2004-06-15
Specially shaped contact via and integrated circuit therewith Grant 6,734,564 - Cronin , et al. May 11, 2	2004-05-11
Specially shaped contact via and integrated circuit therewith App 20040046258 - Cronin, John Edward ; et al.	2004-03-11
One-mask metal-insulator-metal capacitor and method for forming same App 20030178696 - Adler, Eric ; et al.	2003-09-25
Dual damascene horn antenna App 20020149530 - Ballantine, Arne Watson ; et al.	2002-10-17
Method and apparatus for making air gap insulation for semiconductor devices App 20020145201 - Armbrust, Douglas Scott ; et al.	2002-10-10
One-mask metal-insulator-metal capacitor and method for forming same Grant 6,452,779 - Adler , et al. September 17, 2	2002-09-17
Reduced electromigration and stressed induced migration of Cu wires by surface coating App 20020098681 - Hu, Chao-Kun ; et al.	2002-07-25
Reduced electromigration and stressed induced migration of Cu wires by surface coating Grant 6,342,733 - Hu , et al. January 29, 2	2002-01-29
Plasma treatment to enhance inorganic dielectric adhesion to copper App 20010053591 - Buchwalter, Leena P. ; et al.	2001-12-20
Method for making a finger capacitor with tuneable dielectric constant Grant 6,303,456 - Pricer , et al. October 16, 2	2001-10-16
Plasma treatment to enhance inorganic dielectric adhesion to copper Grant 6,261,951 - Buchwalter , et al. July 17, 2	2001-07-17
Process of making a microcavity structure and applications thereof Grant 5,773,361 - Cronin , et al. June 30, 1	1998-06-30