Srivastava; Rajeev

Patent Applications and Registrations

Patent applications and USPTO patent grants for Srivastava; Rajeev.The latest application filed is for "systems and methods for obfuscating a circuit design".

Company Profile

8.9.9

Srivastava; Rajeev - Austin TX
Srivastava; Rajeev - San Jose CA
Srivastava; Rajeev - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems And Methods For Obfuscating A Circuit Design App 20220277126 - Irissou; Bertrand ; et al.	2022-09-01
Systems and methods for obfuscating a circuit design Grant 11,301,609 - Irissou , et al. April 12, 2	2022-04-12
Methods For Engineering Integrated Circuit Design And Development App 20220043956 - Irissou; Bertrand ; et al.	2022-02-10
Systems And Methods For Obfuscating A Circuit Design App 20220027544 - Irissou; Bertrand ; et al.	2022-01-27
Methods for engineering integrated circuit design and development Grant 11,182,526 - Irissou , et al. November 23, 2	2021-11-23
Systems And Methods For Obfuscating A Circuit Design App 20200285795 - Irissou; Bertrand ; et al.	2020-09-10
Systems and methods for obfuscating a circuit design Grant 10,671,700 - Irissou , et al.	2020-06-02
Methods For Engineering Integrated Circuit Design And Development App 20200089833 - Irissou; Bertrand ; et al.	2020-03-19
Systems And Methods For Obfuscating A Circuit Design App 20190392105 - Irissou; Bertrand ; et al.	2019-12-26
Methods for engineering integrated circuit design and development Grant 10,452,802 - Irissou , et al. Oc	2019-10-22
Systems for engineering integrated circuit design and development Grant 10,437,953 - Irissou , et al. O	2019-10-08
Systems and methods for obfuscating a circuit design Grant 10,423,748 - Irissou , et al. Sept	2019-09-24
Methods For Engineering Integrated Circuit Design And Development App 20180011958 - Irissou; Bertrand ; et al.	2018-01-11
Systems And Methods For Obfuscating A Circuit Design App 20180011959 - Irissou; Bertrand ; et al.	2018-01-11
Systems For Engineering Integrated Circuit Design And Development App 20180011948 - Irissou; Bertrand ; et al.	2018-01-11
Visual yield analysis of intergrated circuit layouts Grant 7,886,238 - Sharma , et al. February 8, 2	2011-02-08
Graphical user interface for prototyping early instance density Grant 7,810,063 - Sharma , et al. October 5, 2	2010-10-05
Automatic placement of decoupling capacitors Grant 7,600,208 - Sharma , et al. October 6, 2	2009-10-06

Company Registrations

SEC

0001303234

Srivastava Rajeev

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