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name:-0.012359142303467
name:-0.027817010879517
name:-0.0093710422515869
Srinivasan; Sankaranarayanan Patent Filings

Srinivasan; Sankaranarayanan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Srinivasan; Sankaranarayanan.The latest application filed is for "machine-learning enhanced compiler".

Company Profile
7.21.8
  • Srinivasan; Sankaranarayanan - Bangalore IN
  • Srinivasan; Sankaranarayanan - San Jose CA
  • Srinivasan; Sankaranarayanan - Karnataka Bangalore IN
  • Srinivasan; Sankaranarayanan - Boulder CO
  • Srinivasan; Sankaranarayanan - Longmont CO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of generating an antibody naive library, said library and application(s) thereof
Grant 11,384,354 - Chatterjee , et al. July 12, 2
2022-07-12
Machine-learning enhanced compiler
Grant 11,366,948 - Srinivasan , et al. June 21, 2
2022-06-21
Afucosylated protein, cell expressing said protein and associated methods
Grant 11,267,899 - Chatterjee , et al. March 8, 2
2022-03-08
Method of generating a synthetic antibody library, said library and application(s) thereof
Grant 11,230,706 - Chatterjee , et al. January 25, 2
2022-01-25
Machine-learning Enhanced Compiler
App 20210117601 - SRINIVASAN; Sankaranarayanan ;   et al.
2021-04-22
Dna-binding Domain Of Crispr System, Non-fucosylated And Partially Fucosylated Proteins, And Methods Thereof
App 20200339666 - Prasad; Bhargav ;   et al.
2020-10-29
A Method Of Generating An Antibody Na Ve Library, Said Library And Application(s) Thereof
App 20200283757 - CHATTERJEE; Sohang ;   et al.
2020-09-10
DNA-binding domain of CRISPR system, non-fucosylated and partially fucosylated proteins, and methods thereof
Grant 10,752,674 - Prasad , et al. A
2020-08-25
A Method Of Generating A Synthetic Antibody Library, Said Library And Application(s) Thereof
App 20200149032 - CHATTERJEE; Sohang ;   et al.
2020-05-14
Vectors For Cloning And Expression Of Proteins, Methods And Applications Thereof
App 20190119691 - CHATTERJEE; Sohang ;   et al.
2019-04-25
Dna-binding Domain Of Crispr System, Non-fucosylated And Partially Fucosylated Proteins, And Methods Thereof
App 20190112358 - Prasad; Bhargav ;   et al.
2019-04-18
Non-fucosylated protein and methods thereof
Grant 10,077,434 - Chatterjee , et al. September 18, 2
2018-09-18
Afucosylated Protein, Cell Expressing Said Protein And Associated Methods
App 20180171028 - Chatterjee; Sohang ;   et al.
2018-06-21
Non-fucosylated Protein And Methods Thereof
App 20170306305 - Chatterjee; Sohang ;   et al.
2017-10-26
Latch based optimization during implementation of circuit designs for programmable logic devices
Grant 8,146,041 - Srinivasan , et al. March 27, 2
2012-03-27
Method and arrangement providing for implementation granularity using implementation sets
Grant 8,141,010 - Kong , et al. March 20, 2
2012-03-20
Circuit design fitting
Grant 8,136,073 - Srinivasan , et al. March 13, 2
2012-03-13
Clock speed for a digital circuit
Grant 8,024,696 - Srinivasan , et al. September 20, 2
2011-09-20
Latch based optimization during implementation of circuit designs for programmable logic devices
Grant 8,010,923 - Srinivasan , et al. August 30, 2
2011-08-30
Merging of equivalent logic blocks in a circuit design
Grant 7,984,415 - Srinivasan July 19, 2
2011-07-19
Placement driven control set resynthesis
Grant 7,979,831 - Srinivasan July 12, 2
2011-07-12
Fanout-optimization during physical synthesis for placed circuit designs
Grant 7,853,914 - Srinivasan , et al. December 14, 2
2010-12-14
Efficient timing graph update for dynamic netlist changes
Grant 7,657,855 - Manaker, Jr. , et al. February 2, 2
2010-02-02
Cost-based performance driven legalization technique for placement in logic designs
Grant 7,636,876 - Srinivasan , et al. December 22, 2
2009-12-22
Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device
Grant 7,392,498 - Srinivasan , et al. June 24, 2
2008-06-24
Method and arrangement providing for implementation granularity using implementation sets
Grant 7,360,177 - Kong , et al. April 15, 2
2008-04-15
Method and system for designing integrated circuits using implementation directives
Grant 7,181,704 - Downs , et al. February 20, 2
2007-02-20
Alleviating timing based congestion within circuit designs
Grant 7,152,217 - Srinivasan December 19, 2
2006-12-19
Using router feedback for placement improvements for logic design
Grant 7,076,758 - Srinivasan , et al. July 11, 2
2006-07-11

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