Srinivasan; Adi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Srinivasan; Adi.The latest application filed is for "thermal simulation using adaptive 3d and hierarchical grid mechanisms".

Company Profile

0.20.7

Srinivasan; Adi - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Thermal simulation using adaptive 3D and hierarchical grid mechanisms Grant 8,286,111 - Chandra , et al. October 9, 2	2012-10-09
Transient thermal analysis Grant 8,019,580 - Chandra , et al. September 13, 2	2011-09-13
Thermally aware design modification Grant 7,823,102 - Chandra , et al. October 26, 2	2010-10-26
Thermal Simulation Using Adaptive 3D and Hierarchical Grid Mechanisms App 20090024347 - Chandra; Rajit ; et al.	2009-01-22
Thermally Aware Design Modification App 20090019411 - Chandra; Rajit ; et al.	2009-01-15
Method And Apparatus For Using Full-chip Thermal Analysis Of Semiconductor Chip Designs To Compute Thermal Conductance App 20080141192 - CHANDRA; RAJIT ; et al.	2008-06-12
Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance Grant 7,353,471 - Chandra , et al. April 1, 2	2008-04-01
Circuit optimization for minimum path timing violations Grant 7,222,318 - Srinivasan May 22, 2	2007-05-22
Method for determining load capacitance Grant 7,003,741 - Srinivasan February 21, 2	2006-02-21
Function block architecture for gate array and method for forming an asic Grant 6,954,917 - How , et al. October 11, 2	2005-10-11
Method for optimal driver selection App 20040210857 - Srinivasan, Adi	2004-10-21
Method for optimal driver selection Grant 6,754,877 - Srinivasan June 22, 2	2004-06-22
Circuit optimization for minimum path timing violations App 20040088664 - Srinivasan, Adi	2004-05-06
Circuit optimization for minimum path timing violations Grant 6,701,505 - Srinivasan March 2, 2	2004-03-02
Method for match delay buffer insertion Grant 6,701,506 - Srinivasan , et al. March 2, 2	2004-03-02
Method for determining a zero-skew buffer insertion point Grant 6,701,507 - Srinivasan March 2, 2	2004-03-02
Method for balanced-delay clock tree insertion Grant 6,698,006 - Srinivasan , et al. February 24, 2	2004-02-24
Function block architecture for gate array Grant 6,690,194 - How , et al. February 10, 2	2004-02-10
Function block architecture for gate array App 20030214324 - How, Dana ; et al.	2003-11-20
Method and apparatus for controlling and observing data in a logic block-based ASIC Grant 6,611,932 - How , et al. August 26, 2	2003-08-26
Method and apparatus for controlling and observing data in a logic block-based asic App 20020073369 - How, Dana ; et al.	2002-06-13
Asic routing architecture Grant 6,242,767 - How , et al. June 5, 2	2001-06-05
Method and apparatus for controlling and observing data in a logic block-based asic Grant 6,223,313 - How , et al. April 24, 2	2001-04-24
Function block architecture for gate array Grant 6,014,038 - How , et al. January 11, 2	2000-01-11
Programmable interconnect architecture using fewer storage cells than switches Grant 5,406,138 - Srinivasan , et al. * April 11, 1	1995-04-11
Reprogrammable interconnect architecture using fewer storage cells than switches Grant 5,319,261 - Srinivasan , et al. June 7, 1	1994-06-07
Static random access memory cell with single logic-high voltage level bit-line and address-line drivers Grant 5,301,147 - Guo , et al. April 5, 1	1994-04-05

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