Speiser; Maya
Patent Applications and Registrations
Patent applications and USPTO patent grants for Speiser; Maya.The latest application filed is for "method and system for embedding wire model objects in a circuit schematic design".
- Speiser; Maya - Tel Aviv-Jaffa IL
| Patent | Date |
|---|---|
| Method and system for enhancing circuit design process Grant 7,331,029 - Amit , et al. February 12, 2 | 2008-02-12 |
| Method and system for modeling wiring routing in a circuit design Grant 7,318,212 - Amit , et al. January 8, 2 | 2008-01-08 |
| Method and system for embedding wire model objects in a circuit schematic design Grant 7,290,235 - Amit , et al. October 30, 2 | 2007-10-30 |
| Method and system for modeling wiring routing in a circuit design App 20070067750 - Amit; Niv ; et al. | 2007-03-22 |
| Method and system for enhancing circuit design process App 20070067748 - Amit; Niv ; et al. | 2007-03-22 |
| Method and system for embedding wire model objects in a circuit schematic design App 20070067749 - Amit; Niv ; et al. | 2007-03-22 |
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