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name:-0.90907692909241
name:-0.30338883399963
name:-0.016132831573486
SPEIER; Thomas Philip Patent Filings

SPEIER; Thomas Philip

Patent Applications and Registrations

Patent applications and USPTO patent grants for SPEIER; Thomas Philip.The latest application filed is for "cache-based trace logging using tags in system memory".

Company Profile
18.52.67
  • SPEIER; Thomas Philip - Wake Forest NC
  • Speier; Thomas Philip - Raleigh NC US
  • Speier; Thomas Philip - Holly Springs NC
  • Speier, Thomas Philip - Holly Spring NC
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Treating Main Memory As A Collection Of Tagged Cache Lines For Trace Logging
App 20220269614 - MOLA; Jordi ;   et al.
2022-08-25
Cache-based Trace Logging Using Tags In An Upper-level Cache
App 20220269604 - MOLA; Jordi ;   et al.
2022-08-25
Cache-based Trace Logging Using Tags In System Memory
App 20220269615 - MOLA; Jordi ;   et al.
2022-08-25
Performing Speculative Address Translation In Processor-based Devices
App 20220261355 - SPEIER; Thomas Philip ;   et al.
2022-08-18
Reach-based explicit dataflow processors, and related computer-readable media and methods
Grant 11,392,537 - Gupta , et al. July 19, 2
2022-07-19
Enabling peripheral device messaging via application portals in processor-based devices
Grant 11,366,769 - Klauser , et al. June 21, 2
2022-06-21
PROCESS DEDICATED IN-MEMORY TRANSLATION LOOKASIDE BUFFERS (TLBs) (mTLBs) FOR AUGMENTING MEMORY MANAGEMENT UNIT (MMU) TLB FOR TRANSLATING VIRTUAL ADDRESSES (VAs) TO PHYSICAL ADDRESSES (PAs) IN A PROCESSOR-BASED SYSTEM
App 20220147463 - VENKATARAMAN; Madhavan Thirukkurungudi ;   et al.
2022-05-12
Obsoleting Values Stored In Registers In A Processor Based On Processing Obsolescent Register-encoded Instructions
App 20220066779 - SARTORIUS; Thomas Andrew ;   et al.
2022-03-03
Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system
Grant 11,232,042 - Venkataraman , et al. January 25, 2
2022-01-25
Ticket based request flow control
Grant 11,226,910 - McDonald , et al. January 18, 2
2022-01-18
Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions
Grant 11,188,334 - Sartorius , et al. November 30, 2
2021-11-30
Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data
Grant 11,126,437 - Sartorius , et al. September 21, 2
2021-09-21
Performing atomic store-and-invalidate operations in processor-based devices
Grant 11,119,770 - Speier , et al. September 14, 2
2021-09-14
Optimizing access to page table entries in processor-based devices
Grant 11,061,820 - Speier July 13, 2
2021-07-13
Method, apparatus, and system for reducing pipeline stalls due to address translation misses
Grant 11,061,822 - Ghoshal , et al. July 13, 2
2021-07-13
Providing Express Memory Obsolescence In Processor-based Devices
App 20210173655 - SARTORIUS; Thomas Andrew ;   et al.
2021-06-10
Obsoleting Values Stored In Registers In A Processor Based On Processing Obsolescent Register-encoded Instructions
App 20210165658 - SARTORIUS; Thomas Andrew ;   et al.
2021-06-03
Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system
Grant 11,016,899 - Sharma , et al. May 25, 2
2021-05-25
PROCESS DEDICATED IN-MEMORY TRANSLATION LOOKASIDE BUFFERS (TLBs) (mTLBs) FOR AUGMENTING MEMORY MANAGEMENT UNIT (MMU) TLB FOR TRANSLATING VIRTUAL ADDRESSES (VAs) TO PHYSICAL ADDRESSES (PAs) IN A PROCESSOR-BASED SYSTEM
App 20210149818 - VENKATARAMAN; Madhavan Thirukkurungudi ;   et al.
2021-05-20
Operand-based reach explicit dataflow processors, and related methods and computer-readable media
Grant 10,956,162 - Clancy , et al. March 23, 2
2021-03-23
Optimizing Access To Page Table Entries In Processor-based Devices
App 20210064537 - SPEIER; Thomas Philip
2021-03-04
Performing Atomic Store-and-invalidate Operations In Processor-based Devices
App 20210026636 - SPEIER; Thomas Philip ;   et al.
2021-01-28
Facilitating page table entry (PTE) maintenance in processor-based devices
Grant 10,896,135 - Robinson , et al. January 19, 2
2021-01-19
Operand-based Reach Explicit Dataflow Processors, And Related Methods And Computer-readable Media
App 20200409712 - CLANCY; Robert Douglas ;   et al.
2020-12-31
Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions
Grant 10,877,895 - Yen , et al. December 29, 2
2020-12-29
Selectively Honoring Speculative Memory Prefetch Requests Based On Bandwidth State Of A Memory Access Path Component(s) In A Processor-based System
App 20200356486 - Sharma; Nikhil Narendradev ;   et al.
2020-11-12
Reach-based Explicit Dataflow Processors, And Related Computer-readable Media And Methods
App 20200301877 - GUPTA; Gagan ;   et al.
2020-09-24
Ticket Based Request Flow Control
App 20200285597 - MCDONALD; Joseph Gerald ;   et al.
2020-09-10
Method, Apparatus, And System For Prefetching Exclusive Cache Coherence State For Store Instructions
App 20200065006 - YEN; Luke ;   et al.
2020-02-27
Method, Apparatus, And System For Memory Bandwidth Aware Data Prefetching
App 20200065247 - CHOUDHARY; Niket ;   et al.
2020-02-27
Method, Apparatus, And System For Reducing Pipeline Stalls Due To Address Translation Misses
App 20200065260 - GHOSHAL; Pritha ;   et al.
2020-02-27
Providing efficient handling of memory array failures in processor-based systems
Grant 10,541,044 - Speier , et al. Ja
2020-01-21
Combining Load Or Store Instructions
App 20200004550 - THAKKER; Harsh ;   et al.
2020-01-02
Method, Apparatus, And System For Storing Memory Encryption Realm Key Ids
App 20190384725 - LASKO; Darren ;   et al.
2019-12-19
Adaptively Predicting Usefulness Of Prefetches Generated By Hardware Prefetch Engines In Processor-based Devices
App 20190370176 - Priyadarshi; Shivam ;   et al.
2019-12-05
Dynamically determining memory attributes in processor-based systems
Grant 10,372,635 - Speier
2019-08-06
Precise invalidation of virtually tagged caches
Grant 10,318,436 - McAvoy , et al.
2019-06-11
Converting A Stale Cache Memory Unique Request To A Read Unique Snoop Response In A Multiple (multi-) Central Processing Unit (cpu) Processor To Reduce Latency Associated With Reissuing The Stale Unique Request
App 20190087333 - Robinson; Eric Francis ;   et al.
2019-03-21
Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems
Grant 10,228,991 - Asbe , et al.
2019-03-12
Precise Invalidation Of Virtually Tagged Caches
App 20190034349 - MCAVOY; William ;   et al.
2019-01-31
Providing Hardware-based Translation Lookaside Buffer (tlb) Conflict Resolution In Processor-based Systems
App 20190004883 - Asbe; Samar ;   et al.
2019-01-03
Preventing the displacement of high temporal locality of reference data fill buffers
Grant 10,114,750 - Clancy , et al. October 30, 2
2018-10-30
Aggregating Cache Maintenance Instructions In Processor-based Devices
App 20180285269 - McAvoy; William James ;   et al.
2018-10-04
Prefetch Mechanisms With Non-equal Magnitude Stride
App 20180173631 - SARTORIUS; Thomas Andrew ;   et al.
2018-06-21
Providing Efficient Handling Of Memory Array Failures In Processor-based Systems
App 20180121274 - Speier; Thomas Philip ;   et al.
2018-05-03
Precise Invalidation Of Virtually Tagged Caches
App 20180089094 - CLANCY; Robert Douglas ;   et al.
2018-03-29
Dynamically Determining Memory Attributes In Processor-based Systems
App 20180060255 - Speier; Thomas Philip
2018-03-01
Optimizing performance for context-dependent instructions
Grant 9,823,929 - Streett , et al. November 21, 2
2017-11-21
Write-allocation For A Cache Based On Execute Permissions
App 20170255569 - SARTORIUS; Thomas Andrew ;   et al.
2017-09-07
Method And Apparatus For Effective Clock Scaling At Exposed Cache Stalls
App 20170090508 - PRIYADARSHI; Shivam ;   et al.
2017-03-30
Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
Grant 9,594,713 - Pascarella , et al. March 14, 2
2017-03-14
Determining Prefetch Instructions Based On Instruction Encoding
App 20170046158 - YEN; Luke ;   et al.
2017-02-16
Method and apparatus for cache tag compression
Grant 9,514,061 - Pellerin, III , et al. December 6, 2
2016-12-06
Method And Apparatus For Cache Tag Compression
App 20160342530 - PELLERIN, III; Henry Arthur ;   et al.
2016-11-24
Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems
Grant 9,329,930 - Ingalls , et al. May 3, 2
2016-05-03
Methods and apparatus for improving performance of semaphore management sequences across a coherent bus
Grant 9,292,442 - Speier , et al. March 22, 2
2016-03-22
Bridging Strongly Ordered Write Transactions To Devices In Weakly Ordered Domains, And Related Apparatuses, Methods, And Computer-readable Media
App 20160077991 - Pascarella; Randall John ;   et al.
2016-03-17
Cache Memory Error Detection Circuits For Detecting Bit Flips In Valid Indicators In Cache Memory Following Invalidate Operations, And Related Methods And Processor-based Systems
App 20150301884 - Ingalls; John Sumner ;   et al.
2015-10-22
Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods
Grant 9,110,830 - Dieffenderfer , et al. August 18, 2
2015-08-18
Enforcing strongly-ordered requests in a weakly-ordered processing
Grant 9,026,744 - Hofmann , et al. May 5, 2
2015-05-05
Direct Snoop Intervention
App 20150074357 - MCDONALD; Joseph G. ;   et al.
2015-03-12
Methods And Apparatus For Improving Performance Of Semaphore Management Sequences Across A Coherent Bus
App 20140310468 - Speier; Thomas Philip ;   et al.
2014-10-16
Optimizing Performance For Context-dependent Instructions
App 20140281405 - Streett; Daren Eugene ;   et al.
2014-09-18
Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions
Grant 8,782,356 - Panavich , et al. July 15, 2
2014-07-15
Method for filtering traffic to a physically-tagged data cache
Grant 8,612,690 - Clancy , et al. December 17, 2
2013-12-17
Method and apparatus for scheduling BIST routines
Grant 8,499,208 - Dieffenderfer , et al. July 30, 2
2013-07-30
Preventing The Displacement Of High Temporal Locality Of Reference Data Fill Buffers
App 20130191559 - Clancy; Robert D. ;   et al.
2013-07-25
Determining Cache Hit/Miss of Aliased Addresses in Virtually-Tagged Cache(s), and Related Systems and Methods
App 20130185520 - Dieffenderfer; James Norris ;   et al.
2013-07-18
Method for Filtering Traffic to a Physically-Tagged Data Cache
App 20130185473 - Clancy; Robert D. ;   et al.
2013-07-18
Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions
App 20130151799 - Panavich; Jason Lawrence ;   et al.
2013-06-13
Methods and apparatus for dynamically managing banked memory
Grant 8,443,162 - Speier , et al. May 14, 2
2013-05-14
Apparatus and methods to reduce castouts in a multi-level cache hierarchy
Grant 8,386,716 - Speier , et al. February 26, 2
2013-02-26
Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
Grant 8,352,682 - Speier , et al. January 8, 2
2013-01-08
Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy
App 20120059995 - Speier; Thomas Philip ;   et al.
2012-03-08
Apparatus and methods to reduce castouts in a multi-level cache hierarchy
Grant 8,078,803 - Speier , et al. December 13, 2
2011-12-13
Apparatus and Methods to Reduce Duplicate Line Fills in a Victim Cache
App 20110202727 - Speier; Thomas Philip ;   et al.
2011-08-18
Methods and Apparatus for Issuing Memory Barrier Commands in a Weakly Ordered Storage System
App 20100306470 - Speier; Thomas Philip ;   et al.
2010-12-02
Promoting a line from shared to exclusive in a cache
Grant 7,752,396 - Dieffenderfer , et al. July 6, 2
2010-07-06
Method and apparatus for performing an atomic semaphore operation
Grant 7,610,463 - Speier , et al. October 27, 2
2009-10-27
Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache
Grant 7,523,265 - Dieffenderfer , et al. April 21, 2
2009-04-21
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
Grant 7,500,045 - Hofmann , et al. March 3, 2
2009-03-03
Promoting a Line from Shared to Exclusive in a Cache
App 20080313410 - Dieffenderfer; James Norris ;   et al.
2008-12-18
Method and apparatus to clear semaphore reservation for exclusive access to shared memory
Grant 7,421,529 - Speier , et al. September 2, 2
2008-09-02
Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy
App 20080183967 - Speier; Thomas Philip ;   et al.
2008-07-31
Method and Apparatus for Scheduling BIST Routines
App 20080115026 - Dieffenderfer; James Norris ;   et al.
2008-05-15
Method and Apparatus for Executing a BIST Routine
App 20080109691 - Dieffenderfer; James Norris ;   et al.
2008-05-08
Method and apparatus for segregating shared and non-shared data in cache memory banks
Grant 7,353,319 - Speier , et al. April 1, 2
2008-04-01
Method and apparatus to clear semaphore reservation
App 20070094430 - Speier; Thomas Philip ;   et al.
2007-04-26
Systems and methods for selectively inclusive cache
App 20070038814 - Dieffenderfer; James Norris ;   et al.
2007-02-15
Method and apparatus for managing cache memory accesses
App 20060277356 - Speier; Thomas Philip ;   et al.
2006-12-07
Ensuring orderly forward progress in granting snoop castout requests
Grant 7,127,562 - Dieffenderfer , et al. October 24, 2
2006-10-24
Enforcing strongly-ordered requests in a weakly-ordered processing system
App 20060218358 - Hofmann; Richard Gerard ;   et al.
2006-09-28
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system
App 20060218335 - Hofmann; Richard Gerard ;   et al.
2006-09-28
Systems and arrangements for promoting a line from shared to exclusive in a cache
App 20060212659 - Dieffenderfer; James Norris ;   et al.
2006-09-21
Methods and apparatus for dynamically managing banked memory
App 20060168390 - Speier; Thomas Philip ;   et al.
2006-07-27
Method and apparatus for performing an atomic semaphore operation
App 20060090051 - Speier; Thomas Philip ;   et al.
2006-04-27
Dynamic cache coherency snooper presence with variable snoop latency
Grant 6,985,972 - Dieffenderfer , et al. January 10, 2
2006-01-10
Random access memory having an adaptable latency
Grant 6,961,276 - Atallah , et al. November 1, 2
2005-11-01
Efficiently calculating a branch target address
Grant 6,948,053 - Augsburg , et al. September 20, 2
2005-09-20
Method for moving snoop pushes to the front of a request queue
Grant 6,907,502 - Augsburg , et al. June 14, 2
2005-06-14
Random access memory having an adaptable latency
App 20050063211 - Atallah, Francois Ibrahim ;   et al.
2005-03-24
Ensuring orderly forward progress in granting snoop castout requests
App 20040255085 - Dieffenderfer, James Norris ;   et al.
2004-12-16
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
Grant 6,816,962 - Augsburg , et al. November 9, 2
2004-11-09
Method for moving snoop pushes to the front of a request queue
App 20040068623 - Augsburg, Victor Roberts ;   et al.
2004-04-08
Dynamic cache coherency snooper presence with variable snoop latency
App 20040068595 - Dieffenderfer, James Norris ;   et al.
2004-04-08
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
App 20030163670 - Augsburg, Victor Roberts ;   et al.
2003-08-28
Efficiently calculating a branch target address
App 20030163677 - Augsburg, Victor Roberts ;   et al.
2003-08-28

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