Speers; Theodore M.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Speers; Theodore M..The latest application filed is for "testability circuits for logic circuit arrays".
- Speers; Theodore M. - San Leandro CA
| Patent | Date |
|---|---|
| Testability circuits for logic circuit arrays Grant 5,614,818 - El Ayat , et al. March 25, 1 | 1997-03-25 |
| Testability circuits for logic arrays Grant 5,528,600 - El Ayat , et al. June 18, 1 | 1996-06-18 |
| Methods for preventing disturbance of antifuses during programming Grant 5,194,759 - El-Ayat , et al. March 16, 1 | 1993-03-16 |
| Methods of reducing anti-fuse resistance during programming Grant 5,126,282 - Chiang , et al. June 30, 1 | 1992-06-30 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 