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name:-0.020282030105591
name:-0.0084209442138672
Spear; Michael B. Patent Filings

Spear; Michael B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Spear; Michael B..The latest application filed is for "reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implem".

Company Profile
6.18.17
  • Spear; Michael B. - Round Rock TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface
Grant 11,099,601 - Carlough , et al. August 24, 2
2021-08-24
Staged power on/off sequence at the I/O phy level in an interchip interface
Grant 10,901,936 - Dreps , et al. January 26, 2
2021-01-26
Reducing chip latency at a clock boundary by reference clock phase adjustment
Grant 10,771,068 - Carlough , et al. Sep
2020-09-08
Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface
Grant 10,698,440 - Carlough , et al.
2020-06-30
Built-in self-test for receiver channel
Grant 10,608,763 - Rell, III , et al.
2020-03-31
Reducing Latency Of Memory Read Operations Returning Data On A Read Data Path Across Multiple Clock Boundaries, To A Host Implem
App 20190384352 - Carlough; Steven R. ;   et al.
2019-12-19
Built-in Self-test For Receiver Channel
App 20190363813 - RELL, III; John G. ;   et al.
2019-11-28
Reducing Chip Latency At A Clock Boundary By Reference Clock Phase Adjustment
App 20190260380 - Carlough; Steven R. ;   et al.
2019-08-22
Reducing Latency Of Memory Read Operations Returning Data On A Read Data Path Across Multiple Clock Boundaries, To A Host Implem
App 20190212769 - Carlough; Steven R. ;   et al.
2019-07-11
Double data rate (DDR) memory read latency reduction
Grant 10,162,773 - Carlough , et al. Dec
2018-12-25
Staged Power On/off Sequence At The I/o Phy Level In An Interchip Interface
App 20180024963 - DREPS; DANIEL M. ;   et al.
2018-01-25
Power reduction in a parallel data communications interface using clock resynchronization
Grant 9,715,270 - Baumgartner , et al. July 25, 2
2017-07-25
Power Reduction in a Parallel Data Communications Interface Using Clock Resynchronization
App 20170153689 - Baumgartner; Steven J. ;   et al.
2017-06-01
Power reduction in a parallel data communications interface using clock resynchronization
Grant 9,474,034 - Baumgartner , et al. October 18, 2
2016-10-18
System and method to inject a bit error on a bus lane
Grant 9,092,312 - Meaney , et al. July 28, 2
2015-07-28
Parallel data communications mechanism having reduced power continuously calibrated lines
Grant 8,898,504 - Baumgartner , et al. November 25, 2
2014-11-25
Dynamic fault detection and repair in a data communications mechanism
Grant 8,767,531 - Ferraiolo , et al. July 1, 2
2014-07-01
System And Method To Inject A Bit Error On A Bus Lane
App 20140173361 - Meaney; Patrick J. ;   et al.
2014-06-19
Calibration of multiple parallel data communications lines for high skew conditions
Grant 8,681,839 - Bulzacchelli , et al. March 25, 2
2014-03-25
Communicating Control Information for a Data Communications Link Via a Line Being Calibrated
App 20130188656 - Ferraiolo; Frank D. ;   et al.
2013-07-25
Parallel Data Communications Mechanism Having Reduced Power Continuously Calibrated Lines
App 20130159761 - Baumgartner; Steven J. ;   et al.
2013-06-20
Dynamic Fault Detection and Repair in a Data Communications Mechanism
App 20120151247 - Ferraiolo; Frank D. ;   et al.
2012-06-14
Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines
App 20120106539 - Ferraiolo; Frank D. ;   et al.
2012-05-03
Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions
App 20120106687 - Bulzacchelli; John F. ;   et al.
2012-05-03
Power-on initialization and test for a cascade interconnect memory system
Grant 8,139,430 - Buchmann , et al. March 20, 2
2012-03-20
Combined alignment scrambler function for elastic interface
Grant 8,001,412 - Ferraiolo , et al. August 16, 2
2011-08-16
Power-on Initialization And Test For A Cascade Interconnect Memory System
App 20100005281 - Buchmann; Peter L. ;   et al.
2010-01-07
Arrangements for Operating In-Line Memory Module Configurations
App 20090276559 - Allen, JR.; James J. ;   et al.
2009-11-05
Combined Alignment Scrambler Function For Elastic Interface
App 20080201599 - Ferraiolo; Frank D. ;   et al.
2008-08-21
Combined alignment scrambler function for elastic interface
Grant 7,412,618 - Ferraiolo , et al. August 12, 2
2008-08-12
Combined alignment scrambler function for elastic interface
App 20060193395 - Ferraiolo; Frank D. ;   et al.
2006-08-31

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