Spadea; Gregorio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Spadea; Gregorio.The latest application filed is for "non-volatile memory including insulated gate bipolar transistors and charge trapping layer containing silicon and nitrogen".

Company Profile

0.8.7

Spadea; Gregorio - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Common source EEPROM and flash memory Grant RE40,976 - Bergemont , et al. November 17, 2	2009-11-17
Non-Volatile Memory Including Insulated Gate Bipolar Transistors And Charge Trapping Layer Containing Silicon and Nitrogen App 20080128794 - Spadea; Gregorio	2008-06-05
Non-volatile memory arrangement having nanocrystals Grant 7,332,769 - Spadea February 19, 2	2008-02-19
Novel applications for insulated gate bipolar transistors App 20070040209 - Spadea; Gregorio	2007-02-22
High voltage N-channel LDMOS devices built in a deep submicron CMOS process App 20060284265 - Spadea; Gregorio	2006-12-21
High voltage N-channel LDMOS devices built in a deep submicron CMOS process App 20060284266 - Spadea; Gregorio	2006-12-21
Low voltage EEPROM memory arrays Grant 7,075,140 - Spadea July 11, 2	2006-07-11
Low voltage EEPROM memory arrays App 20050110073 - Spadea, Gregorio	2005-05-26
Common source EEPROM and flash memory Grant 6,606,265 - Bergemont , et al. August 12, 2	2003-08-12
Common source EEPROM and flash memory App 20020176286 - Bergemont, Albert ; et al.	2002-11-28
High voltage N-channel LDMOS devices built in a deep submicron CMOS process App 20020171103 - Spadea, Gregorio	2002-11-21
Ion implantation method Grant 4,224,733 - Spadea September 30, 1	1980-09-30
Self-aligned CMOS process for bulk silicon and insulating substrate device Grant 4,047,284 - Spadea September 13, 1	1977-09-13
Self-aligned CMOS process for bulk silicon and insulating substrate device Grant 4,043,025 - Spadea August 23, 1	1977-08-23
Self-aligned CMOS process for bulk silicon and insulating substrate device Grant 3,983,620 - Spadea October 5, 1	1976-10-05

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