Sotiriou; Christos P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sotiriou; Christos P..The latest application filed is for "apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection".

Company Profile

0.7.9

Sotiriou; Christos P. - Crete GR
Sotiriou; Christos P. - Heraklion GR
Sotiriou; Christos P. - Heraklion- Crete GR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection Grant 8,074,193 - Sotiriou , et al. December 6, 2	2011-12-06
Apparatus and method for optimizing delay element in asynchronous digital circuits Grant 7,934,186 - Sotiriou , et al. April 26, 2	2011-04-26
Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same Grant 7,870,516 - Sotiriou , et al. January 11, 2	2011-01-11
System and method of determining the speed of digital application specific integrated circuits Grant 7,861,130 - Sotiriou December 28, 2	2010-12-28
Apparatus and Method for Mixed Single-Rail and Dual-Rail Combinational Logic with Completion Detection App 20100231261 - Sotiriou; Christos P. ; et al.	2010-09-16
System and method of determining the speed of digital application specific integrated circuits Grant 7,711,513 - Sotiriou May 4, 2	2010-05-04
Asynchronous, multi-rail digital circuit with gating and gated sub-circuits and method for designing the same Grant 7,603,635 - Sotiriou , et al. October 13, 2	2009-10-13
Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same App 20090183126 - Sotiriou; Christos P. ; et al.	2009-07-16
System and method for reducing EME emissions in digital desynchronized circuits App 20090167380 - Sotiriou; Christos P.	2009-07-02
Apparatus And Method For Optimizing Delay Element In Asynchronous Digital Circuits App 20090108900 - SOTIRIOU; Christos P. ; et al.	2009-04-30
Asynchronous, Multi-rail Digital Circuit With Gating And Gated Sub-circuits And Method For Designing The Same App 20090037853 - SOTIRIOU; Christos P. ; et al.	2009-02-05
System and method of determining the speed of digital application specific integrated circuits App 20080288203 - Sotiriou; Christos P.	2008-11-20
System and method of determining the speed of digital application specific integrated circuits Grant 7,318,003 - Sotiriou January 8, 2	2008-01-08
System and method of determining the speed of digital application specific integrated circuits App 20060217919 - Sotiriou; Christos P.	2006-09-28
Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same App 20060190852 - Sotiriou; Christos P.	2006-08-24
System and method of determining the speed of digital application specific integrated circuits App 20060156050 - Sotiriou; Christos P.	2006-07-13

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