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Model order reduction in transistor level timing
Grant 10,949,593 - Allen , et al. March 16, 2 | 2021-03-16 |
Model Order Reduction In Transistor Level Timing
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Model order reduction in transistor level timing
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Model Order Reduction In Transistor Level Timing
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Model order reduction in transistor level timing
Grant 10,031,988 - Allen , et al. July 24, 2 | 2018-07-24 |
Model Order Reduction In Transistor Level Timing
App 20160085890 - ALLEN; Robert J. ; et al. | 2016-03-24 |
Modeling loading effects of a transistor network
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Delay model construction in the presence of multiple input switching events
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Delay Model Construction In The Presence Of Multiple Input Switching Events
App 20120266119 - Soreff; Jeffrey P. ; et al. | 2012-10-18 |
Timing point selection for a static timing analysis in the presence of interconnect electrical elements
Grant 8,201,120 - Soreff , et al. June 12, 2 | 2012-06-12 |
System and method for common history pessimism relief during static timing analysis
Grant 8,141,014 - Foreman , et al. March 20, 2 | 2012-03-20 |
Device history based delay variation adjustment during static timing analysis
Grant 8,108,816 - Foreman , et al. January 31, 2 | 2012-01-31 |
Modeling Loading Effects of a Transistor Network
App 20110224965 - Hathaway; David J. ; et al. | 2011-09-15 |
Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements
App 20110167395 - Soreff; Jeffrey P. ; et al. | 2011-07-07 |
System And Method For Common History Pessimism Relief During Static Timing Analysis
App 20110035714 - Foreman; Eric A. ; et al. | 2011-02-10 |
System and method for improved hierarchical analysis of electronic circuits
Grant 7,870,515 - Shephard, III , et al. January 11, 2 | 2011-01-11 |
System And Method For Device History Based Delay Variation Adjustment During Static Timing Analysis
App 20100318951 - Foreman; Eric A. ; et al. | 2010-12-16 |
System and Method for Improved Hierarchical Analysis of Electronic Circuits
App 20090183130 - Shephard, III; Philip G. ; et al. | 2009-07-16 |
Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
Grant 7,325,210 - Rao , et al. January 29, 2 | 2008-01-29 |
Multiple mode approach to building static timing models for digital transistor circuits
App 20070234253 - Soreff; Jeffrey P. ; et al. | 2007-10-04 |
Methods for modeling latch transparency
Grant 7,225,419 - Behnen , et al. May 29, 2 | 2007-05-29 |
Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
App 20060206845 - Rao; Vasant ; et al. | 2006-09-14 |
Methods for modeling latch transparency
Grant 7,080,335 - Behnen , et al. July 18, 2 | 2006-07-18 |
Methods for modeling latch transparency
App 20050071790 - Behnen, Erwin ; et al. | 2005-03-31 |
Methods for modeling latch transparency
App 20050071794 - Behnen, Erwin ; et al. | 2005-03-31 |
Method for reducing RC parasitics in interconnect networks of an integrated circuit
Grant 6,763,504 - Rao , et al. July 13, 2 | 2004-07-13 |
Reduced pessimism clock gating tests for a timing analysis tool
Grant 6,718,523 - Hathaway , et al. April 6, 2 | 2004-04-06 |
Reduced pessimism clock gating tests for a timing analysis tool
App 20030009733 - Hathaway, David J. ; et al. | 2003-01-09 |
Method for evaluating the timing of digital machines with statistical variability in their delays
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