| Patent | Date |
|---|
Three-dimensional (3D) integrated circuit device having a backside power delivery network
Grant 11,444,068 - Song , et al. September 13, 2 | 2022-09-13 |
Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits
Grant 11,437,379 - Song , et al. September 6, 2 | 2022-09-06 |
Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods
Grant 11,404,374 - Lim , et al. August 2, 2 | 2022-08-02 |
Integrated Circuit (ic) Packages Employing Front Side Back-end-of-line (fs-beol) To Back Side Back-end-of-line (bs-beol) Stacking For Three-dimensional (3d) Die Stacking, And Related Fabrication Methods
App 20220165707 - Song; Stanley Seungchul ; et al. | 2022-05-26 |
Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure
Grant 11,310,911 - Song , et al. April 19, 2 | 2022-04-19 |
Hybrid conductor integration in power rail
Grant 11,302,638 - Zhu , et al. April 12, 2 | 2022-04-12 |
Circuits Employing A Back Side-front Side Connection Structure For Coupling Back Side Routing To Front Side Routing, And Related Complementary Metal Oxide Semiconductor (cmos) Circuits And Methods
App 20220102266 - Lim; Hyeokjin ; et al. | 2022-03-31 |
Field-effect Transistors (fet) Circuits Employing Topside And Backside Contacts For Topside And Backside Routing Of Fet Power And Logic Signals, And Related Complementary Metal Oxide Semiconductor (cmos) Circuits
App 20220093594 - SONG; Stanley Seungchul ; et al. | 2022-03-24 |
Stacked Die Integrated With Package Voltage Regulators
App 20220077109 - CHAVA; Bharani ; et al. | 2022-03-10 |
Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow organization, and related methods
Grant 11,270,991 - Chava , et al. March 8, 2 | 2022-03-08 |
INTEGRATED CIRCUITS (ICs) EMPLOYING FRONT SIDE (FS) BACK END-OF-LINE (BEOL) (FS-BEOL) INPUT/OUTPUT (I/O) ROUTING AND BACK SIDE (BS) BEOL (BS-BEOL) POWER ROUTING FOR CURRENT FLOW ORGANIZATION, AND RELATED METHODS
App 20220068906 - Chava; Bharani ; et al. | 2022-03-03 |
Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication
Grant 11,257,917 - Yuan , et al. February 22, 2 | 2022-02-22 |
Intertwined well connection and decoupling capacitor layout structure for integrated circuits
Grant 11,244,895 - Manchana , et al. February 8, 2 | 2022-02-08 |
Gate-all-around (gaa) Transistors With Shallow Source/drain Regions And Methods Of Fabricating The Same
App 20220037493 - Feng; Peijie ; et al. | 2022-02-03 |
Backside Power Distribution Network (pdn) Processing
App 20220028758 - SONG; Stanley Seungchul ; et al. | 2022-01-27 |
Three-dimensional (3d) Integrated Circuit (ic) Integration Of An Embedded Chip And A Preformed Metal Routing Structure
App 20220022315 - SONG; Stanley Seungchul ; et al. | 2022-01-20 |
Three-dimensional (3d) Integrated Circuit Device Having A Backside Power Delivery Network
App 20220020735 - SONG; Stanley Seungchul ; et al. | 2022-01-20 |
Gate-all-around (gaa) Transistors With Additional Bottom Channel For Reduced Parasitic Capacitance And Methods Of Fabrication
App 20210384310 - Yuan; Jun ; et al. | 2021-12-09 |
Metal filling in a dielectric layer under metal layer one (M1)and above an active device layer in semiconductor devices
Grant 11,195,793 - Chava , et al. December 7, 2 | 2021-12-07 |
Intertwined Well Connection And Decoupling Capacitor Layout Structure For Integrated Circuits
App 20210375747 - MANCHANA; Ramesh ; et al. | 2021-12-02 |
Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
Grant 11,152,347 - Song , et al. October 19, 2 | 2021-10-19 |
Field effect transistor (FET) comprising channels with silicon germanium (SiGe)
Grant 11,145,654 - Lim , et al. October 12, 2 | 2021-10-12 |
Hybrid Conductor Integration In Power Rail
App 20210217699 - ZHU; John Jianhong ; et al. | 2021-07-15 |
Metal Filling Under M1 Layer Of Semiconductor Devices
App 20210217697 - CHAVA; Bharani ; et al. | 2021-07-15 |
Sensor for gate leakage detection
Grant 10,996,261 - Park , et al. May 4, 2 | 2021-05-04 |
FIELD EFFECT TRANSISTOR (FET) COMPRISING CHANNELS WITH SILICON GERMANIUM (SiGe)
App 20210118883 - LIM; Kwanyong ; et al. | 2021-04-22 |
Integrated Device Comprising A Cmos Structure Comprising Well-less Transistors
App 20210057410 - SONG; Stanley Seungchul ; et al. | 2021-02-25 |
Bulk acoustic wave (BAW) and passive-on-glass (POG) filter co-integration
Grant 10,840,884 - Song , et al. November 17, 2 | 2020-11-17 |
Circuits Having A Diffusion Break With Avoided Or Reduced Adjacent Semiconductor Channel Strain Relaxation, And Related Methods
App 20200303550 - Song; Stanley Seungchul ; et al. | 2020-09-24 |
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
Grant 10,763,364 - Song , et al. Sep | 2020-09-01 |
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
Grant 10,700,204 - Song , et al. | 2020-06-30 |
Standard cell architecture with M1 layer unidirectional routing
Grant 10,593,700 - Gupta , et al. | 2020-03-17 |
Circuits Having A Diffusion Break With Avoided Or Reduced Adjacent Semiconductor Channel Strain Relaxation, And Related Methods
App 20200058792 - Song; Stanley Seungchul ; et al. | 2020-02-20 |
Sensor For Gate Leakage Detection
App 20200049757 - PARK; Hyunwoo ; et al. | 2020-02-13 |
Bulk Acoustic Wave (baw) And Passive-on-glass (pog) Filter Co-integration
App 20190363694 - SONG; Stanley Seungchul ; et al. | 2019-11-28 |
Cell Circuits Formed In Circuit Cells Employing Offset Gate Cut Areas In A Non-active Area For Routing Transistor Gate Cross-con
App 20190319022 - Song; Stanley Seungchul ; et al. | 2019-10-17 |
Integrated circuits including a FinFET and a nanostructure FET
Grant 10,439,039 - Song , et al. O | 2019-10-08 |
Hybrid Metal Interconnect Structures For Advanced Process Nodes
App 20190304919 - ZHU; John ; et al. | 2019-10-03 |
Systems And Methods For Dummy Gate Tie-offs In A Self-aligned Gate Contact (sagc) Cell
App 20190296126 - Song; Stanley Seungchul ; et al. | 2019-09-26 |
Modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area
Grant 10,418,244 - Song , et al. Sept | 2019-09-17 |
High Density And Reliable Vertical Natural Capacitors
App 20190206984 - BAO; Junjing ; et al. | 2019-07-04 |
Middle-of-line (mol) Metal Resistor Temperature Sensors For Localized Temperature Sensing Of Active Semiconductor Areas In Integ
App 20190195700 - Ge; Lixin ; et al. | 2019-06-27 |
High density and reliable vertical natural capacitors
Grant 10,325,979 - Bao , et al. | 2019-06-18 |
Bulk Finfet With Self-aligned Bottom Isolation
App 20190157160 - LU; Cimang ; et al. | 2019-05-23 |
Adaptive pulse generation circuits for clocking pulse latches with minimum hold time
Grant 10,291,211 - Song , et al. | 2019-05-14 |
Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs)
Grant 10,247,617 - Ge , et al. | 2019-04-02 |
Nanowire Device With Reduced Parasitics
App 20190067435 - Badaroglu; Mustafa ; et al. | 2019-02-28 |
Metal Layers For A Three-port Bit Cell
App 20190035796 - Mojumder; Niladri Narayan ; et al. | 2019-01-31 |
Hybrid coloring methodology for multi-pattern technology
Grant 10,175,571 - Chen , et al. J | 2019-01-08 |
Semiconductor device having an airgap defined at least partially by a protective structure
Grant 10,163,792 - Zhu , et al. Dec | 2018-12-25 |
Nanowire device with reduced parasitics
Grant 10,157,992 - Badaroglu , et al. Dec | 2018-12-18 |
Metal layers for a three-port bit cell
Grant 10,141,317 - Mojumder , et al. Nov | 2018-11-27 |
Semiconductor device having a gap defined therein
Grant 10,079,293 - Xu , et al. September 18, 2 | 2018-09-18 |
Vertically stacked nanowire field effect transistors
Grant 10,043,796 - Machkaoutsan , et al. August 7, 2 | 2018-08-07 |
Seven-transistor static random-access memory bitcell with reduced read disturbance
Grant 10,037,795 - Jung , et al. July 31, 2 | 2018-07-31 |
Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices
Grant 10,032,678 - Xu , et al. July 24, 2 | 2018-07-24 |
Modified Self-aligned Quadruple Patterning (saqp) Processes Using Cut Pattern Masks To Fabricate Integrated Circuit (ic) Cells With Reduced Area
App 20180204765 - Song; Stanley Seungchul ; et al. | 2018-07-19 |
Variable interconnect pitch for improved performance
Grant 9,984,029 - Rim , et al. May 29, 2 | 2018-05-29 |
Standard Cell Architecture With M1 Layer Unidirectional Routing
App 20180122824 - GUPTA; Mukul ; et al. | 2018-05-03 |
Semiconductor Device Having A Gap Defined Therein
App 20180114848 - Xu; Jeffrey Junhao ; et al. | 2018-04-26 |
Contact wrap around structure
Grant 9,953,979 - Xu , et al. April 24, 2 | 2018-04-24 |
Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
Grant 9,941,154 - Song , et al. April 10, 2 | 2018-04-10 |
Adaptive Pulse Generation Circuits For Clocking Pulse Latches With Minimum Hold Time
App 20180069535 - Song; Stanley Seungchul ; et al. | 2018-03-08 |
MIDDLE-OF-LINE (MOL) METAL RESISTOR TEMPERATURE SENSORS FOR LOCALIZED TEMPERATURE SENSING OF ACTIVE SEMICONDUCTOR AREAS IN INTEGRATED CIRCUITS (ICs)
App 20180058943 - Ge; Lixin ; et al. | 2018-03-01 |
Standard cell architecture with M1 layer unidirectional routing
Grant 9,887,209 - Gupta , et al. February 6, 2 | 2018-02-06 |
Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
Grant 9,876,017 - Mojumder , et al. January 23, 2 | 2018-01-23 |
Semiconductor device having a gap defined therein
Grant 9,871,121 - Xu , et al. January 16, 2 | 2018-01-16 |
Integrated circuits having reduced dimensions between components
Grant 9,859,210 - Song , et al. January 2, 2 | 2018-01-02 |
Device and method to connect gate regions separated using a gate cut
Grant 9,853,112 - Liu , et al. December 26, 2 | 2017-12-26 |
Heterogeneous Cell Array
App 20170338215 - Song; Stanley Seungchul ; et al. | 2017-11-23 |
Adjacent device isolation
Grant 9,824,936 - Machkaoutsan , et al. November 21, 2 | 2017-11-21 |
Static random-access memory (SRAM) sensor for bias temperature instability
Grant 9,812,188 - Mojumder , et al. November 7, 2 | 2017-11-07 |
Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods
Grant 9,806,083 - Mojumder , et al. October 31, 2 | 2017-10-31 |
Self-aligned structure
Grant 9,799,560 - Song , et al. October 24, 2 | 2017-10-24 |
Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices
Grant 9,793,164 - Machkaoutsan , et al. October 17, 2 | 2017-10-17 |
Integrated Circuits Including A Finfet And A Nanostructure Fet
App 20170278842 - Song; Stanley Seungchul ; et al. | 2017-09-28 |
Fin With An Epitaxial Cladding Layer
App 20170236841 - Song; Stanley Seungchul ; et al. | 2017-08-17 |
Vertically Stacked Nanowire Field Effect Transistors
App 20170221884 - Machkaoutsan; Vladimir ; et al. | 2017-08-03 |
Integrated circuit devices and methods
Grant 9,721,891 - Xu , et al. August 1, 2 | 2017-08-01 |
NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE EMPLOYING RECESSED CONDUCTIVE STRUCTURES FOR CONDUCTIVELY COUPLING NANOWIRE STRUCTURES
App 20170207313 - Song; Stanley Seungchul ; et al. | 2017-07-20 |
Fin-type device system and method
Grant 9,698,267 - Song , et al. July 4, 2 | 2017-07-04 |
Conductive cap for metal-gate transistor
Grant 9,698,232 - Yang , et al. July 4, 2 | 2017-07-04 |
Nanowire Device With Reduced Parasitics
App 20170186846 - Badaroglu; Mustafa ; et al. | 2017-06-29 |
Merging lithography processes for gate patterning
Grant 9,691,868 - Song , et al. June 27, 2 | 2017-06-27 |
NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES
App 20170170268 - Song; Stanley Seungchul ; et al. | 2017-06-15 |
Reduced height M1 metal lines for local on-chip routing
Grant 9,666,481 - Song , et al. May 30, 2 | 2017-05-30 |
Voltage scaling for holistic energy management
Grant 9,660,649 - Mojumder , et al. May 23, 2 | 2017-05-23 |
Self-aligned Metal Cut And Via For Back-end-of-line (beol) Processes For Semiconductor Integrated Circuit (ic) Fabrication, And Related Processes And Devices
App 20170140986 - Machkaoutsan; Vladimir ; et al. | 2017-05-18 |
Middle-of-line integration methods and semiconductor devices
Grant 9,653,399 - Zhu , et al. May 16, 2 | 2017-05-16 |
Reverse Self Aligned Double Patterning Process For Back End Of Line Fabrication Of A Semiconductor Device
App 20170110364 - Song; Stanley Seungchul ; et al. | 2017-04-20 |
Nanowire Channel Structures Of Continuously Stacked Heterogeneous Nanowires For Complementary Metal Oxide Semiconductor (cmos) Devices
App 20170110541 - Xu; Jeffrey Junhao ; et al. | 2017-04-20 |
Nanowire Channel Structures Of Continuously Stacked Nanowires For Complementary Metal Oxide Semiconductor (cmos) Devices
App 20170110374 - Xu; Jeffrey Junhao ; et al. | 2017-04-20 |
Method And Apparatus For Source-drain Junction Formation In A Finfet With In-situ Doping
App 20170104088 - MACHKAOUTSAN; Vladimir ; et al. | 2017-04-13 |
Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
Grant 9,620,454 - Zhu , et al. April 11, 2 | 2017-04-11 |
Integrated Circuit Devices And Methods
App 20170092587 - Xu; Jeffrey Junhao ; et al. | 2017-03-30 |
Off-center gate cut
Grant 9,607,988 - Liu , et al. March 28, 2 | 2017-03-28 |
Multi-cell Transistor Device And Method Of Making Same With Cut Polyoxide Process For Self-aligned Contacts
App 20170077090 - SONG; Stanley Seungchul ; et al. | 2017-03-16 |
Method for asymmetrical geometrical scaling
Grant 9,594,864 - Song , et al. March 14, 2 | 2017-03-14 |
Metal Layers For A Three-port Bit Cell
App 20170062439 - Mojumder; Niladri Narayan ; et al. | 2017-03-02 |
Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
Grant 9,564,361 - Song , et al. February 7, 2 | 2017-02-07 |
Method and apparatus for source-drain junction formation in a FinFET with in-situ doping
Grant 9,564,518 - Machkaoutsan , et al. February 7, 2 | 2017-02-07 |
Adjacent Device Isolation
App 20170033020 - MACHKAOUTSAN; Vladimir ; et al. | 2017-02-02 |
Device And Method To Connect Gate Regions Separated Using A Gate Cut
App 20170018620 - Liu; Yanxiang ; et al. | 2017-01-19 |
User experience based management technique for mobile system-on-chips
Grant 9,542,518 - Mojumder , et al. January 10, 2 | 2017-01-10 |
Integrated circuit devices and methods
Grant 9,543,248 - Xu , et al. January 10, 2 | 2017-01-10 |
Three-port bit cell having increased width
Grant 9,536,596 - Mojumder , et al. January 3, 2 | 2017-01-03 |
Hybrid Coloring Methodology For Multi-pattern Technology
App 20160370699 - CHEN; Xiangdong ; et al. | 2016-12-22 |
Integrated Circuits Having Reduced Dimensions Between Components
App 20160372414 - Song; Stanley Seungchul ; et al. | 2016-12-22 |
Metal layers for a three-port bit cell
Grant 9,524,972 - Mojumder , et al. December 20, 2 | 2016-12-20 |
Conductive layer routing
Grant 9,508,589 - Song , et al. November 29, 2 | 2016-11-29 |
Structure For Coupling Metal Layer Interconnects In A Semiconductor Device
App 20160343661 - GUPTA; Mukul ; et al. | 2016-11-24 |
Electron-beam (E-beam) based semiconductor device features
Grant 9,502,283 - Song , et al. November 22, 2 | 2016-11-22 |
Adjacent device isolation
Grant 9,502,414 - Machkaoutsan , et al. November 22, 2 | 2016-11-22 |
Sub-fin device isolation
Grant 9,496,181 - Song , et al. November 15, 2 | 2016-11-15 |
Method Of Forming Fins From Different Materials On A Substrate
App 20160322391 - SONG; Stanley Seungchul ; et al. | 2016-11-03 |
Method For Asymmetrical Geometrical Scaling
App 20160314235 - SONG; Stanley Seungchul ; et al. | 2016-10-27 |
Capacitor from second level middle-of-line layer in combination with decoupling capacitors
Grant 9,478,490 - Zhu , et al. October 25, 2 | 2016-10-25 |
Half node scaling for vertical structures
Grant 9,478,541 - Song , et al. October 25, 2 | 2016-10-25 |
Systems and methods of forming a reduced capacitance device
Grant 9,472,453 - Xu , et al. October 18, 2 | 2016-10-18 |
Self-aligned Structure
App 20160293485 - Song; Stanley Seungchul ; et al. | 2016-10-06 |
SRAM read buffer with reduced sensing delay and improved sensing margin
Grant 9,460,777 - Jung , et al. October 4, 2 | 2016-10-04 |
Selective Analog And Radio Frequency Performance Modification
App 20160284595 - GENG; Chunqi ; et al. | 2016-09-29 |
Shared global read and write word lines
Grant 9,455,026 - Mojumder , et al. September 27, 2 | 2016-09-27 |
Conductive Cap For Metal-gate Transistor
App 20160276455 - Yang; Haining ; et al. | 2016-09-22 |
Adjacent Device Isolation
App 20160254261 - MACHKAOUTSAN; Vladimir ; et al. | 2016-09-01 |
Electron-beam (e-beam) Based Semiconductor Device Features
App 20160247714 - Song; Stanley Seungchul ; et al. | 2016-08-25 |
Static Random-access Memory (sram) Sensor
App 20160247554 - Mojumder; Niladri Narayan ; et al. | 2016-08-25 |
Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation
Grant 9,424,909 - Mojumder , et al. August 23, 2 | 2016-08-23 |
Middle-of-line Integration Methods And Semiconductor Devices
App 20160240485 - Zhu; John Jianhong ; et al. | 2016-08-18 |
Metal Layers For A Three-port Bit Cell
App 20160240539 - Mojumder; Niladri Narayan ; et al. | 2016-08-18 |
Reduced Height M1 Metal Lines For Local On-chip Routing
App 20160240437 - SONG; Stanley Seungchul ; et al. | 2016-08-18 |
Integrated Circuit Device Including Multiple Via Connectors And A Metal Structure Having A Ladder Shape
App 20160233159 - Song; Stanley Seungchul ; et al. | 2016-08-11 |
Off-center Gate Cut
App 20160225767 - Liu; Yanxiang ; et al. | 2016-08-04 |
Integrated Circuit Devices And Methods
App 20160211216 - Xu; Jeffrey Junhao ; et al. | 2016-07-21 |
Method of forming fins from different materials on a substrate
Grant 9,396,931 - Song , et al. July 19, 2 | 2016-07-19 |
System and method to regulate operating voltage of a memory array
Grant 9,378,803 - Song , et al. June 28, 2 | 2016-06-28 |
Static random-access memory (SRAM) array
Grant 9,379,014 - Mojumder , et al. June 28, 2 | 2016-06-28 |
Grounding dummy gate in scaled layout design
Grant 9,379,058 - Song , et al. June 28, 2 | 2016-06-28 |
Sub-fin Device Isolation
App 20160181161 - SONG; Stanley Seungchul ; et al. | 2016-06-23 |
Strapped Contact In A Semiconductor Device
App 20160163646 - Yang; Haining ; et al. | 2016-06-09 |
Static Random Access Memory (sram) Bit Cells With Wordlines On Separate Metal Layers For Increased Performance, And Related Methods
App 20160163713 - Mojumder; Niladri Narayan ; et al. | 2016-06-09 |
Static Random Access Memory (sram) Bit Cells With Wordline Landing Pads Split Across Boundary Edges Of The Sram Bit Cells
App 20160163714 - Mojumder; Niladri Narayan ; et al. | 2016-06-09 |
Contact Wrap Around Structure
App 20160148936 - XU; Jeffrey Junhao ; et al. | 2016-05-26 |
Reduced height M1 metal lines for local on-chip routing
Grant 9,349,686 - Song , et al. May 24, 2 | 2016-05-24 |
Shared Global Read And Write Word Lines
App 20160141021 - Mojumder; Niladri Narayan ; et al. | 2016-05-19 |
User Experience Based Management Technique For Mobile System-on-chips
App 20160140275 - Mojumder; Niladri Narayan ; et al. | 2016-05-19 |
Voltage Scaling For Holistic Energy Management
App 20160142054 - Mojumder; Niladri Narayan ; et al. | 2016-05-19 |
Barrier Structure
App 20160141250 - Bao; Junjing ; et al. | 2016-05-19 |
Fin Field-effect Transistor Static Random Access Memory Devices With P-channel Metal-oxide-semiconductor Pass Gate Transistors
App 20160133634 - MOJUMDER; Niladri Narayan ; et al. | 2016-05-12 |
Threshold Voltage Adjustment In Metal Oxide Semiconductor Field Effect Transistor With Silicon Oxynitride Polysilicon Gate Stack On Fully Depleted Silicon-on-insulator
App 20160133722 - SONG; Stanley Seungchul ; et al. | 2016-05-12 |
Silicon germanium read port for a static random access memory register file
Grant 9,336,864 - Mojumder , et al. May 10, 2 | 2016-05-10 |
Dual write wordline memory cell
Grant 9,336,863 - Jung , et al. May 10, 2 | 2016-05-10 |
Methods Of Forming A Metal-insulator-semiconductor (mis) Structure And A Dual Contact Device
App 20160126144 - Xu; Jeffrey Junhao ; et al. | 2016-05-05 |
High density static random access memory array having advanced metal patterning
Grant 9,318,564 - Mojumder , et al. April 19, 2 | 2016-04-19 |
Seven-transistor Static Random-access Memory Bitcell With Reduced Read Disturbance
App 20160093365 - SONG; Stanley Seungchul ; et al. | 2016-03-31 |
Selective Current Boosting In A Static Random-access Memory
App 20160093364 - JUNG; Seong-Ook ; et al. | 2016-03-31 |
Method And Apparatis For Source-drain Junction Formation Finfet With Quantum Barrier And Ground Plane Doping
App 20160087070 - MACHKAOUTSAN; Vladimir ; et al. | 2016-03-24 |
Metal-gate With An Amorphous Metal Layer
App 20160086805 - Xu; Jeffrey Junhao ; et al. | 2016-03-24 |
Tie-off Structures For Middle-of-line (mol) Manufactured Integrated Circuits, And Related Methods
App 20160079167 - Zhu; John Jianhong ; et al. | 2016-03-17 |
MIDDLE-OF-LINE (MOL) MANUFACTURED INTEGRATED CIRCUITS (ICs) EMPLOYING LOCAL INTERCONNECTS OF METAL LINES USING AN ELONGATED VIA, AND RELATED METHODS
App 20160079175 - Zhu; John Jianhong ; et al. | 2016-03-17 |
Half Node Scaling For Vertical Structures
App 20160071847 - SONG; Stanley Seungchul ; et al. | 2016-03-10 |
Capacitor From Second Level Middle-of-line Layer In Combination With Decoupling Capacitors
App 20160071795 - ZHU; John Jianhong ; et al. | 2016-03-10 |
Silicon Germanium Read Port For A Static Random Access Memory Register File
App 20160064068 - Mojumder; Niladri ; et al. | 2016-03-03 |
Three-port Bit Cell Having Increased Width
App 20160064067 - Mojumder; Niladri Narayan ; et al. | 2016-03-03 |
Fin Field-effect Transistor Static Random Access Memory Devices With P-channel Metal-oxide-semiconductor Pass Gate Transistors
App 20160043092 - MOJUMDER; Niladri Narayan ; et al. | 2016-02-11 |
Heterogeneous channel material integration into wafer
Grant 9,257,407 - Song , et al. February 9, 2 | 2016-02-09 |
Silicon germanium FinFET formation by Ge condensation
Grant 9,257,556 - Xu , et al. February 9, 2 | 2016-02-09 |
Stress In N-channel Field Effect Transistors
App 20160035891 - XU; Jeffrey Junhao ; et al. | 2016-02-04 |
Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator
Grant 9,252,228 - Song , et al. February 2, 2 | 2016-02-02 |
Semiconductor Device Having An Airgap Defined At Least Partially By A Protective Structure
App 20160027726 - Zhu; John Jianhong ; et al. | 2016-01-28 |
Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
Grant 9,245,975 - Lim , et al. January 26, 2 | 2016-01-26 |
Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
Grant 9,240,404 - Lim , et al. January 19, 2 | 2016-01-19 |
Self-aligned Via For Gate Contact Of Semiconductor Devices
App 20160005822 - SONG; Stanley Seungchul ; et al. | 2016-01-07 |
Dual Write Wordline Memory Cell
App 20150380080 - Jung; Seong-Ook ; et al. | 2015-12-31 |
Method Of Forming Finfet Having Fins Of Different Height
App 20150380257 - SONG; Stanley Seungchul | 2015-12-31 |
Via material selection and processing
Grant 9,196,583 - Zhu , et al. November 24, 2 | 2015-11-24 |
High Density Static Random Access Memory Array Having Advanced Metal Patterning
App 20150333131 - MOJUMDER; Niladri ; et al. | 2015-11-19 |
Standard Cell Architecture With M1 Layer Unidirectional Routing
App 20150333008 - GUPTA; Mukul ; et al. | 2015-11-19 |
Via Material Selection And Processing
App 20150325515 - ZHU; John Jianhong ; et al. | 2015-11-12 |
High Density Sram Array Design With Skipped, Inter-layer Conductive Contacts
App 20150325514 - MOJUMDER; Niladri Narayan ; et al. | 2015-11-12 |
Data Path System On Chip Design Methodology
App 20150317426 - SONG; Stanley Seungchul ; et al. | 2015-11-05 |
Variable Interconnect Pitch For Improved Performance
App 20150301973 - RIM; Kern ; et al. | 2015-10-22 |
Complementarily strained FinFET structure
Grant 9,165,929 - Rim , et al. October 20, 2 | 2015-10-20 |
Method of forming finFET having fins of different height
Grant 9,159,576 - Song October 13, 2 | 2015-10-13 |
Fin-type semiconductor device
Grant 9,153,587 - Li , et al. October 6, 2 | 2015-10-06 |
Methods Of Forming A Metal-insulator-semiconductor (mis) Structure And A Dual Contact Device
App 20150270134 - Xu; Jeffrey Junhao ; et al. | 2015-09-24 |
Reduced Height M1 Metal Lines For Local On-chip Routing
App 20150262930 - SONG; Stanley Seungchul ; et al. | 2015-09-17 |
Systems And Methods Of Forming A Reduced Capacitance Device
App 20150262875 - Xu; Jeffrey Junhao ; et al. | 2015-09-17 |
Semiconductor Device Having A Gap Defined Therein
App 20150255571 - Xu; Jeffrey Junhao ; et al. | 2015-09-10 |
Grounding Dummy Gate In Scaled Layout Design
App 20150235948 - SONG; Stanley Seungchul ; et al. | 2015-08-20 |
Conductive Layer Routing
App 20150194339 - SONG; Stanley Seungchul ; et al. | 2015-07-09 |
Silicon Germanium Finfet Formation By Ge Condensation
App 20150194525 - XU; Jeffrey Junhao ; et al. | 2015-07-09 |
Fin-type Semiconductor Device
App 20150187774 - Li; Xia ; et al. | 2015-07-02 |
Threshold Voltage Adjustment In Metal Oxide Semiconductor Field Effect Transistor With Silicon Oxynitride Polysilicon Gate Stack On Fully Depleted Silicon-on-insulator
App 20150155364 - SONG; Stanley Seungchul ; et al. | 2015-06-04 |
Complementarily Strained Finfet Structure
App 20150144962 - RIM; Kern ; et al. | 2015-05-28 |
Merging Lithography Processes For Gate Patterning
App 20150145070 - SONG; Stanley Seungchul ; et al. | 2015-05-28 |
Heterogeneous Channel Material Integration Into Wafer
App 20150115473 - SONG; Stanley Seungchul ; et al. | 2015-04-30 |
Fin-type semiconductor device
Grant 8,999,792 - Li , et al. April 7, 2 | 2015-04-07 |
Reverse Self Aligned Double Patterning Process For Back End Of Line Fabrication Of A Semiconductor Device
App 20150076704 - Song; Stanley Seungchul ; et al. | 2015-03-19 |
Method Of Forming Fins From Different Materials On A Substrate
App 20150035019 - Song; Stanley Seungchul ; et al. | 2015-02-05 |
Sram Read Buffer With Reduced Sensing Delay And Improved Sensing Margin
App 20150036417 - Jung; Seong-Ook ; et al. | 2015-02-05 |
Recessed Channel Insulated-gate Field Effect Transistor With Self-aligned Gate And Increased Channel Length
App 20150037952 - Lim; Kwan-Yong ; et al. | 2015-02-05 |
Embedded Polysilicon Resistor In Integrated Circuits Formed By A Replacement Gate Process
App 20150008531 - LIM; Kwan-Yong ; et al. | 2015-01-08 |
Fin-type Device System And Method
App 20140313821 - SONG; Stanley Seungchul ; et al. | 2014-10-23 |
Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
Grant 8,865,549 - Lim , et al. October 21, 2 | 2014-10-21 |
Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
Grant 8,865,542 - Lim , et al. October 21, 2 | 2014-10-21 |
Fin-type Semiconductor Device
App 20140264485 - Li; Xia ; et al. | 2014-09-18 |
System And Method To Regulate Operating Voltage Of A Memory Array
App 20140269020 - Song; Stanley Seungchul ; et al. | 2014-09-18 |
Method Of Forming Finfet Having Fins Of Different Height
App 20140252474 - Song; Stanley Seungchul | 2014-09-11 |
Methods for designing fin-based field effect transistors (FinFETS)
Grant 8,799,847 - Song , et al. August 5, 2 | 2014-08-05 |
Embedded Polysilicon Resistor in Integrated Circuits Formed by a Replacement Gate Process
App 20140183657 - Lim; Kwan-Yong ; et al. | 2014-07-03 |
Recessed Channel Insulated-Gate Field Effect Transistor with Self-Aligned Gate and Increased Channel Length
App 20140159142 - Lim; Kwan-Yong ; et al. | 2014-06-12 |
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