Song; Chi Jung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Song; Chi Jung.The latest application filed is for "bump structure and fabrication method thereof".

Company Profile

0.10.5

Song; Chi Jung - Daejeon-si KR
Song; Chi-Jung - Daejeon KR
Song; Chi-Jung - Daejon KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bump structure and fabrication method thereof Grant 8,237,276 - Song , et al. August 7, 2	2012-08-07
Bump Structure And Fabrication Method Thereof App 20110285015 - Song; Chi Jung ; et al.	2011-11-24
Method for fabricating an image sensor mounted by mass reflow Grant 7,491,572 - Kim , et al. February 17, 2	2009-02-17
Image sensor mounted by mass reflow App 20070085180 - Kim; Jong-Heon ; et al.	2007-04-19
Area array type semiconductor package fabrication method Grant 7,122,401 - Song October 17, 2	2006-10-17
Semiconductor substrate and land grid array semiconductor package using same and fabrication methods thereof Grant 6,682,957 - Song January 27, 2	2004-01-27
Encapsulation method for ball grid array semiconductor package App 20020148112 - Heo, Seong-Jae ; et al.	2002-10-17
Semiconductor substrate and land grid array semiconductor package using same and fabrication methods thereof App 20020151112 - Song, Chi-Jung	2002-10-17
Semiconductor substrate and land grid array semiconductor package using same Grant 6,441,498 - Song August 27, 2	2002-08-27
Area array type semiconductor package and fabrication method App 20020038904 - Song, Chi-Jung	2002-04-04
Area array type semiconductor package and fabrication method Grant 6,316,837 - Song November 13, 2	2001-11-13
Package body and semiconductor chip package using same Grant 6,031,284 - Song February 29, 2	2000-02-29
Semiconductor chip stack package Grant 5,910,682 - Song June 8, 1	1999-06-08
Semiconductor package having leads with step-shaped dimples Grant 5,834,837 - Song November 10, 1	1998-11-10
Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package Grant 5,770,888 - Song , et al. June 23, 1	1998-06-23

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.