SON; Jae Ick

Patent Applications and Registrations

Patent applications and USPTO patent grants for SON; Jae Ick.The latest application filed is for "semiconductor device".

Company Profile

2.7.9

SON; Jae Ick - Hwaseong-si KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Device App 20220084859 - SON; Jae Ick ; et al.	2022-03-17
Semiconductor device Grant 11,201,069 - Son , et al. December 14, 2	2021-12-14
Semiconductor device Grant 11,195,587 - Son , et al. December 7, 2	2021-12-07
Semiconductor Device App 20210090663 - SON; Jae Ick ; et al.	2021-03-25
Semiconductor Device App 20210090922 - SON; Jae Ick ; et al.	2021-03-25
Method and system for verifying layout of integrated circuit including vertical memory cells Grant 10,140,415 - Lee , et al. Nov	2018-11-27
Method of verifying layout of vertical memory device Grant 9,929,172 - Kim , et al. March 27, 2	2018-03-27
Memory device having cell over periphery (COP) structure, memory package and method of manufacturing the same Grant 9,799,672 - Son , et al. October 24, 2	2017-10-24
Method And System For Verifying Layout Of Integrated Circuit Including Vertical Memory Cells App 20170255742 - Lee; Jae-eun ; et al.	2017-09-07
Method Of Verifying Layout Of Vertical Memory Device App 20170243882 - KIM; KI-WON ; et al.	2017-08-24
Memory Device Having Cell Over Periphery (cop) Structure, Memory Package And Method Of Manufacturing The Same App 20160307910 - SON; Jae-Ick ; et al.	2016-10-20

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