| Patent | Date |
|---|
Method and apparatus for implementing two architectures in a chip
Grant 7,343,479 - Knebel , et al. March 11, 2 | 2008-03-11 |
Architectural support for selective use of high-reliability mode in a computer system
Grant 7,287,185 - Safford , et al. October 23, 2 | 2007-10-23 |
Systems and methods for variable control of power dissipation in a pipelined processor
Grant 7,281,147 - Soltis, Jr. , et al. October 9, 2 | 2007-10-09 |
System and method for utilizing a scoreboard to indicate information pertaining to pending register writes
Grant 7,243,215 - Arnold , et al. July 10, 2 | 2007-07-10 |
Off-chip lockstep checking
Grant 7,237,144 - Safford , et al. June 26, 2 | 2007-06-26 |
System and method for providing predicate data to multiple pipeline stages
Grant 7,213,132 - Benjamin , et al. May 1, 2 | 2007-05-01 |
Processing system and method for efficiently enabling detection of data hazards for long latency instructions
Grant 7,146,490 - Arnold , et al. December 5, 2 | 2006-12-05 |
Masking error detection/correction latency in multilevel cache transfers
Grant 6,874,116 - Walker , et al. March 29, 2 | 2005-03-29 |
System and method for coalescing data utilized to detect data hazards
Grant 6,728,868 - Arnold , et al. April 27, 2 | 2004-04-27 |
Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form
Grant 6,721,875 - McCormick, Jr. , et al. April 13, 2 | 2004-04-13 |
Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data
Grant 6,715,060 - Arnold , et al. March 30, 2 | 2004-03-30 |
Non-speculative instruction fetch in speculative processing
Grant 6,711,671 - Undy , et al. March 23, 2 | 2004-03-23 |
System and method for detecting data hazards within an instruction group of a compiled computer program
Grant 6,711,670 - Soltis, Jr. , et al. March 23, 2 | 2004-03-23 |
System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error
Grant 6,651,164 - Soltis, Jr. , et al. November 18, 2 | 2003-11-18 |
Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs
Grant 6,643,762 - Arnold , et al. November 4, 2 | 2003-11-04 |
System and method for providing predicate data
Grant 6,622,238 - Benjamin , et al. September 16, 2 | 2003-09-16 |
Superscalar processing system and method for selectively stalling instructions within an issue group
Grant 6,618,802 - Arnold , et al. September 9, 2 | 2003-09-09 |
Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information
Grant 6,618,801 - Knebel , et al. September 9, 2 | 2003-09-09 |
System and method for utilizing instruction attributes to detect data hazards
Grant 6,604,192 - Arnold , et al. August 5, 2 | 2003-08-05 |
Masking error detection/correction latency in multilevel cache transfers
Grant 6,591,393 - Walker , et al. July 8, 2 | 2003-07-08 |
Preventing write-after-write data hazards by canceling earlier write when no intervening instruction uses value to be written by the earlier write
Grant 6,470,445 - Arnold , et al. October 22, 2 | 2002-10-22 |
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