Sohn; Dong-Kyun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sohn; Dong-Kyun.The latest application filed is for "semiconductor devices including source/drain stressors and methods of manufacturing the same".

Company Profile

0.28.27

Sohn; Dong-Kyun - Seongnam-si KR
Sohn; Dong-Kyun - Gyeonggi-do KR
Sohn; Dong Kyun - Singapore N/A SG
Sohn; Dong Kyun - Chungcheongbuk-do KR
Sohn; Dong-Kyun - Cheongju KR
Sohn; Dong Kyun - Daejeon KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor devices including raised source/drain stressors and methods of manufacturing the same Grant 9,502,413 - Lim , et al. November 22, 2	2016-11-22
Semiconductor devices having contacts with intervening spacers and method for fabricating the same Grant 9,425,148 - Kim , et al. August 23, 2	2016-08-23
Semiconductor Devices Including Source/drain Stressors And Methods Of Manufacturing The Same App 20150357329 - Lim; Se-Chan ; et al.	2015-12-10
Integrated circuit system employing alternating conductive layers Grant 9,147,654 - Sheng , et al. September 29, 2	2015-09-29
Semiconductor Devices Including Source/drain Stressors And Methods Of Manufacturing The Same App 20130320457 - Lim; Se-Chan ; et al.	2013-12-05
Semiconductor Devices And Method For Fabricating The Same App 20130248990 - KIM; Ho-Jun ; et al.	2013-09-26
Integrated Circuit System Including Nitride Layer Technology App 20130034954 - Nagarad; Sripad Sheshagiri ; et al.	2013-02-07
Integrated circuit system employing low-k dielectrics and method of manufacture thereof Grant 8,358,007 - Sohn , et al. January 22, 2	2013-01-22
Integrated circuit system including nitride layer technology Grant 8,283,263 - Nagarad , et al. October 9, 2	2012-10-09
Reliable memory cell Grant 8,034,670 - Phua , et al. October 11, 2	2011-10-11
Selective STI stress relaxation through ion implantation Grant 8,008,744 - Teo , et al. August 30, 2	2011-08-30
Selective stress relaxation of contact etch stop layer through layout design Grant 7,888,214 - Teo , et al. February 15, 2	2011-02-15
Integrated Circuit System Employing Low-k Dielectrics And Method Of Manufacture Thereof App 20100314763 - Sohn; Dong Kyun ; et al.	2010-12-16
Reliable Memory Cell App 20100230744 - Phua; Timothy ; et al.	2010-09-16
Selective Sti Stress Relaxation Through Ion Implantation App 20100230777 - TEO; Lee Wee ; et al.	2010-09-16
Selective STI stress relaxation through ion implantation Grant 7,727,856 - Teo , et al. June 1, 2	2010-06-01
Method to fabricate variable work function gates for FUSI devices Grant 7,645,687 - Chong , et al. January 12, 2	2010-01-12
Integrated Circuit System Employing Alternating Conductive Layers App 20100001370 - Sheng; Haifeng ; et al.	2010-01-07
Process integration scheme of SONOS technology Grant 7,585,746 - Jung , et al. September 8, 2	2009-09-08
Method For Forming High-k Charge Storage Device App 20090023280 - ANG; Chew-Hoe ; et al.	2009-01-22
Method for forming high-K charge storage device Grant 7,479,425 - Ang , et al. January 20, 2	2009-01-20
Selective STI Stress Relaxation Through Ion Implantation App 20080150037 - Teo; Lee Wee ; et al.	2008-06-26
Semiconductor Device With Doped Transistor App 20080087958 - Verma; Purakh Raj ; et al.	2008-04-17
Implantation-less approach to fabricating strained semiconductor on isolation wafers Grant 7,338,886 - Liu , et al. March 4, 2	2008-03-04
Integrated Circuit System Including Nitride Layer Technology App 20080032513 - Nagarad; Sripad Sheshagiri ; et al.	2008-02-07
Semiconductor device and fabrication method Grant 7,326,609 - Verma , et al. February 5, 2	2008-02-05
Process integration scheme of SONOS technology App 20080014707 - Jung; Sung Mun ; et al.	2008-01-17
Laser activation of implanted contact plug for memory bitline fabrication Grant 7,256,112 - Chong , et al. August 14, 2	2007-08-14
Selective stress relaxation of contact etch stop layer through layout design App 20070132032 - Teo; Lee Wee ; et al.	2007-06-14
Method of forming ultra thin silicon oxynitride for gate dielectric applications Grant 7,202,164 - Liu , et al. April 10, 2	2007-04-10
Method to fabricate Ge and Si devices together for performance enhancement Grant 7,202,140 - Ang , et al. April 10, 2	2007-04-10
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch Grant 7,166,522 - Liu , et al. January 23, 2	2007-01-23
Semiconductor Device And Fabrication Method App 20060252188 - Verma; Purakh Raj ; et al.	2006-11-09
Implantation-less approach to fabricating strained semiconductor on isolation wafers App 20060234479 - Liu; Jinping ; et al.	2006-10-19
Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics App 20060166435 - Teo; Lee Wee ; et al.	2006-07-27
Laser activation of implanted contact plug for memory bitline fabrication App 20060160343 - Chong; Yung Fu ; et al.	2006-07-20
Method to fabricate variable work function gates for FUSI devices App 20060160290 - Chong; Yung Fu ; et al.	2006-07-20
Method for forming high-K charge storage device App 20060160303 - Ang; Chew-Hoe ; et al.	2006-07-20
Method of forming ultra thin silicon oxynitride for gate dielectric applications App 20060110865 - Liu; Jinping ; et al.	2006-05-25
Method for SONOS EFLASH integrated circuit Grant 7,029,976 - Nagarad , et al. April 18, 2	2006-04-18
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch Grant 6,995,078 - Liu , et al. February 7, 2	2006-02-07
Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses Grant 6,946,349 - Lee , et al. September 20, 2	2005-09-20
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch App 20050164473 - Liu, Jin Ping ; et al.	2005-07-28
Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch App 20050164436 - Liu, Jin Ping ; et al.	2005-07-28
Semiconductor device including ternary phase diffusion barrier Grant 6,885,103 - Sohn , et al. April 26, 2	2005-04-26
Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier App 20040017010 - Sohn, Dong Kyun ; et al.	2004-01-29
Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier Grant 6,649,520 - Sohn , et al. November 18, 2	2003-11-18
Semiconductor device having a gate and fabrication method therefor App 20020034868 - Park, Ji Soo ; et al.	2002-03-21
Method for fabricating polycide dual gate in semiconductor device App 20010006832 - Bae, Jong Uk ; et al.	2001-07-05
Method for fabricating thin film at high temperature Grant 6,251,780 - Sohn , et al. June 26, 2	2001-06-26
Method of forming polycide Grant 6,177,335 - Park , et al. January 23, 2	2001-01-23
Method for forming epitaxial Co self-align silicide for semiconductor device Grant 6,077,750 - Sohn , et al. June 20, 2	2000-06-20

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