Sodani; Avinash

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sodani; Avinash.The latest application filed is for "system and method to manage power throttling".

Company Profile

23.59.76

Sodani; Avinash - San Jose CA
Sodani; Avinash - Portland OR
Sodani; Avinash - Hillsboro OR
Sodani; Avinash - Madison WI

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and methods for mesh architecture for high bandwidth multicast and broadcast network Grant 11,455,575 - Tu , et al. September 27, 2	2022-09-27
System And Method To Manage Power Throttling App 20220244767 - Sodani; Avinash ; et al.	2022-08-04
Architecture to support synchronization between core and inference engine for machine learning Grant 11,403,561 - Sodani , et al. August 2, 2	2022-08-02
System And Method For Handling Floating Point Hardware Exception App 20220188108 - Chen; Chia-Hsin ; et al.	2022-06-16
System And Method For Handling Floating Point Hardware Exception App 20220188111 - Chen; Chia-Hsin ; et al.	2022-06-16
System And Method For Handling Floating Point Hardware Exception App 20220188109 - Chen; Chia-Hsin ; et al.	2022-06-16
System And Method For Handling Floating Point Hardware Exception App 20220188110 - Chen; Chia-Hsin ; et al.	2022-06-16
System and method to manage power throttling Grant 11,340,673 - Sodani , et al. May 24, 2	2022-05-24
Method And System For Topk Operation App 20220129270 - Sodani; Avinash ; et al.	2022-04-28
System and method for handling floating point hardware exception Grant 11,301,247 - Chen , et al. April 12, 2	2022-04-12
Architecture of crossbar of inference engine Grant 11,256,517 - Sodani , et al. February 22, 2	2022-02-22
Power Management And Transitioning Cores Within A Multicore System From Idle Mode To Operational Mode Over A Period Of Time App 20220043503 - Chen; Chia-Hsin ; et al.	2022-02-10
Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction Grant 11,210,105 - Sodani December 28, 2	2021-12-28
Power management and transitioning cores within a multicore system from idle mode to operational mode over a period of time Grant 11,181,967 - Chen , et al. November 23, 2	2021-11-23
System And Method For Int9 Quantization App 20210342734 - Sodani; Avinash ; et al.	2021-11-04
Power Management And Staggering Transitioning From Idle Mode To Operational Mode App 20210318740 - Sripada; Srinivas ; et al.	2021-10-14
Queueing System with Head-of-Line Block Avoidance App 20210320880 - SODANI; Avinash ; et al.	2021-10-14
Architecture To Support Tanh And Sigmoid Operations For Inference Acceleration In Machine Learning App 20210248497 - SODANI; Avinash ; et al.	2021-08-12
Power Management And Transitioning Cores Within A Multicore System From Idle Mode To Operational Mode Over A Period Of Time App 20210247836 - Chen; Chia-Hsin ; et al.	2021-08-12
Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine Grant 11,086,633 - Sodani , et al. August 10, 2	2021-08-10
Architecture To Support Color Scheme-based Synchronization For Machine Learning App 20210240521 - SODANI; Avinash ; et al.	2021-08-05
Architecture For Table-based Mathematical Operations For Inference Acceleration In Machine Learning App 20210209492 - Sodani; Avinash ; et al.	2021-07-08
System And Method For Handling Floating Point Hardware Exception App 20210191719 - Chen; Chia-Hsin ; et al.	2021-06-24
System And Methods For Tag-based Synchronization Of Tasks For Machine Learning Operations App 20210191787 - Sodani; Avinash ; et al.	2021-06-24
Architecture for irregular operations in machine learning inference engine Grant 11,029,963 - Sodani , et al. June 8, 2	2021-06-08
Architecture to support color scheme-based synchronization for machine learning Grant 11,016,801 - Sodani , et al. May 25, 2	2021-05-25
Architecture to support tanh and sigmoid operations for inference acceleration in machine learning Grant 10,997,510 - Sodani , et al. May 4, 2	2021-05-04
Address Interleaving For Machine Learning App 20210117866 - Sodani; Avinash ; et al.	2021-04-22
Systems and methods for programmable hardware architecture for machine learning Grant 10,970,080 - Sodani , et al. April 6, 2	2021-04-06
Architecture To Support Synchronization Between Core And Inference Engine For Machine Learning App 20210081846 - Sodani; Avinash ; et al.	2021-03-18
Array-based Inference Engine For Machine Learning App 20210055934 - Sodani; Avinash ; et al.	2021-02-25
Address interleaving for machine learning Grant 10,929,778 - Sodani , et al. February 23, 2	2021-02-23
Architecture for table-based mathematical operations for inference acceleration in machine learning Grant 10,929,760 - Sodani , et al. February 23, 2	2021-02-23
Architecture to support synchronization between core and inference engine for machine learning Grant 10,929,779 - Sodani , et al. February 23, 2	2021-02-23
Architecture for dense operations in machine learning inference engine Grant 10,896,045 - Sodani , et al. January 19, 2	2021-01-19
Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction Grant 10,891,136 - Sodani January 12, 2	2021-01-12
Array-based inference engine for machine learning Grant 10,824,433 - Sodani , et al. November 3, 2	2020-11-03
Providing Multiple Memory Modes For A Processor Including Internal Memory App 20190286559 - Sodani; Avinash ; et al.	2019-09-19
Streaming Engine For Machine Learning Architecture App 20190244117 - SODANI; Avinash ; et al.	2019-08-08
Systems And Methods For Programmable Hardware Architecture For Machine Learning App 20190244141 - SODANI; Avinash ; et al.	2019-08-08
Architecture Of Crossbar Of Inference Engine App 20190244118 - SODANI; Avinash ; et al.	2019-08-08
Architecture For Dense Operations In Machine Learning Inference Engine App 20190244130 - SODANI; Avinash ; et al.	2019-08-08
Architecture For Irregular Operations In Machine Learning Infference Engine App 20190243871 - SODANI; Avinash ; et al.	2019-08-08
Single Instruction Set Architecture (isa) Format For Multiple Isas In Machine Learning Inference Engine App 20190243653 - SODANI; Avinash ; et al.	2019-08-08
Array-based Inference Engine For Machine Learning App 20190243800 - SODANI; Avinash ; et al.	2019-08-08
Providing multiple memory modes for a processor including internal memory Grant 10,346,300 - Sodani , et al. July 9, 2	2019-07-09
Thermal throttling of electronic devices Grant 10,275,001 - Kam , et al.	2019-04-30
Minimizing snoop traffic locally and across cores on a chip multi-core fabric Grant 10,102,129 - Vinod , et al. October 16, 2	2018-10-16
Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture Grant 9,898,351 - Chaffin , et al. February 20, 2	2018-02-20
Scalable event handling in multi-threaded processor cores Grant 9,886,396 - Gramunt , et al. February 6, 2	2018-02-06
Providing Multiple Memory Modes For A Processor Including Internal Memory App 20170357580 - Sodani; Avinash ; et al.	2017-12-14
Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias Grant 9,836,399 - Vinod , et al. December 5, 2	2017-12-05
Physical reference list for tracking physical register sharing Grant 9,733,939 - Kadgi , et al. August 15, 2	2017-08-15
Providing multiple memory modes for a processor including internal memory Grant 9,720,827 - Sodani , et al. August 1, 2	2017-08-01
Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture App 20170185458 - Chaffin; Benjamin C. ; et al.	2017-06-29
Minimizing Snoop Traffic Locally And Across Cores On A Chip Multi-core Fabric App 20170177483 - Vinod; Krishna N. ; et al.	2017-06-22
Providing Thread Fairness In A Hyper-threaded Microprocessor App 20170161106 - Marden; Morris ; et al.	2017-06-08
Controlling non-redundant execution in a redundant multithreading (RMT) processor Grant 9,594,648 - Hinton , et al. March 14, 2	2017-03-14
Thermal Throttling Of Electronic Devices App 20160378149 - Kam; Timothy Y. ; et al.	2016-12-29
Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements Grant 9,524,191 - Marden , et al. December 20, 2	2016-12-20
Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources Grant 9,507,596 - Jagannathan , et al. November 29, 2	2016-11-29
Mechanism To Avoid Hot-L1/Cold-L2 Events In An Inclusive L2 Cache Using L1 Presence Bits For Victim Selection Bias App 20160283380 - Vinod; Krishna N. ; et al.	2016-09-29
Hybrid Memory Architecture App 20160224252 - Hutsell; Steven R. ; et al.	2016-08-04
Scalable Event Handling In Multi-threaded Processor Cores App 20160179533 - Gramunt; Roger ; et al.	2016-06-23
Providing Multiple Memory Modes For A Processor Including Internal Memory App 20160140039 - Sodani; Avinash ; et al.	2016-05-19
Instruction And Logic For Prefetcher Throttling Based On Data Source App 20160062768 - Jagannathan; Ashok ; et al.	2016-03-03
Obtaining data for redundant multithreading (RMT) execution Grant 9,081,688 - Hinton , et al. July 14, 2	2015-07-14
Technique to perform three-source operations Grant 8,825,989 - Sodani , et al. September 2, 2	2014-09-02
Redundant multithreading processor Grant 8,793,689 - Hinton , et al. July 29, 2	2014-07-29
Processor With Second Jump Execution Unit For Branch Misprediction App 20140195790 - Merten; Matthew C. ; et al.	2014-07-10
Physical Reference List for Tracking Physical Register Sharing App 20140095838 - KADGI; VIJAYKUMAR VIJAY ; et al.	2014-04-03
Technique To Perform Three-source Operations App 20140052963 - Sodani; Avinash ; et al.	2014-02-20
Technique to perform three-source operations Grant 8,589,663 - Sodani , et al. November 19, 2	2013-11-19
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Grant 8,521,993 - Marden , et al. August 27, 2	2013-08-27
Managing multiple threads in a single pipeline Grant 8,504,804 - Merten , et al. August 6, 2	2013-08-06
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor Grant 8,438,369 - Marden , et al. May 7, 2	2013-05-07
Managing multiple threads in a single pipeline Grant 8,402,253 - Merten , et al. March 19, 2	2013-03-19
Managing Multiple Threads In A Single Pipeline App 20130013898 - Merten; Matthew ; et al.	2013-01-10
Redundant Multithreading Processor App 20110307894 - Hinton; Glenn J. ; et al.	2011-12-15
Providing Thread Fairness In A Hyper-threaded Microprocessor App 20110055525 - Marden; Morris ; et al.	2011-03-03
Providing Thread Fairness In A Hyper-threaded Microprocessor App 20110055524 - Marden; Morris ; et al.	2011-03-03
Obtaining data for redundant multithreading (RMT) execution App 20100169582 - Hinton; Glenn J. ; et al.	2010-07-01
Controlling non-redundant execution in a redundant multithreading (RMT) processor App 20100169628 - Hinton; Glenn J. ; et al.	2010-07-01
Tracking an oldest processor event using information stored in a register and queue entry Grant 7,721,076 - Sodani , et al. May 18, 2	2010-05-18
Register alias table cache to map a logical register to a physical register Grant 7,711,898 - Sodani , et al. May 4, 2	2010-05-04
Speculatively scheduling micro-operations after allocation Grant 7,600,103 - Sodani , et al. October 6, 2	2009-10-06
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions Grant 7,562,206 - Sodani , et al. July 14, 2	2009-07-14
Late allocation of registers Grant 7,529,913 - Sodani , et al. May 5, 2	2009-05-05
Method and apparatus for rescheduling operations in a processor Grant 7,502,912 - Sodani , et al. March 10, 2	2009-03-10
Method and apparatus for microarchitecture partitioning of execution clusters Grant 7,475,225 - Jourdan , et al. January 6, 2	2009-01-06
Staggered execution stack for vector processing Grant 7,457,938 - Jourdan , et al. November 25, 2	2008-11-25
Providing thread fairness in a hyper-threaded microprocessor App 20080250233 - Marden; Morris ; et al.	2008-10-09
Flow optimization and prediction for VSSE memory operations Grant 7,404,065 - Jourdan , et al. July 22, 2	2008-07-22
Mechanism and method to track oldest processor event App 20080148282 - Sodani; Avinash ; et al.	2008-06-19
Determination of cache entry for future operation Grant 7,363,430 - Samaan , et al. April 22, 2	2008-04-22
Providing temporary storage for contents of configuration registers App 20080082791 - Chennupaty; Srinivas ; et al.	2008-04-03
Managing multiple threads in a single pipeline App 20080082796 - Merten; Matthew ; et al.	2008-04-03
Technique to clear bogus instructions from a processor pipeline App 20080072019 - Sodani; Avinash ; et al.	2008-03-20
Speculatively scheduling micro-operations after allocation App 20080005535 - Sodani; Avinash ; et al.	2008-01-03
Technique to perform three-source operations App 20070300049 - Sodani; Avinash ; et al.	2007-12-27
Vector length tracking mechanism App 20070283129 - Jourdan; Stephan ; et al.	2007-12-06
Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures Grant 7,272,701 - Sodani September 18, 2	2007-09-18
Microarchitecture prediction of execution clusters and inter-cluster communications App 20070157008 - Sodani; Avinash ; et al.	2007-07-05
Method and apparatus for microarchitecture partitioning of execution clusters App 20070157006 - Jourdan; Stephan J. ; et al.	2007-07-05
Flow optimization and prediction for VSSE memory operations App 20070143575 - Jourdan; Stephen ; et al.	2007-06-21
Staggered execution stack for vector processing App 20070079179 - Jourdan; Stephan ; et al.	2007-04-05
Wakeup mechanisms for schedulers App 20070043932 - Kulkarni; Rahul ; et al.	2007-02-22
Early misprediction recovery through periodic checkpoints App 20070043934 - Sodani; Avinash ; et al.	2007-02-22
Method and system for transforming memory location references in instructions Grant 7,174,428 - Hily , et al. February 6, 2	2007-02-06
Determination of cache entry for future operation App 20060230228 - Samaan; Samie B. ; et al.	2006-10-12
Dynamic online optimizer App 20050149912 - Farcy, Alexandre J. ; et al.	2005-07-07
Method and apparatus for rescheduling operations in a processor App 20050149689 - Sodani, Avinash ; et al.	2005-07-07
Method and system for memory renaming App 20050149702 - Hily, Sebastien ; et al.	2005-07-07
Register alias table cache App 20050138338 - Sodani, Avinash ; et al.	2005-06-23
Register file cache App 20050138297 - Sodani, Avinash ; et al.	2005-06-23
System and method for instruction rescheduling App 20050138290 - Hammarlund, Per H. ; et al.	2005-06-23
Late allocation of registers App 20050138334 - Sodani, Avinash ; et al.	2005-06-23
Method and apparatus for limiting ports in a register alias table App 20050091475 - Sodani, Avinash	2005-04-28
Method and system for multiple branch paths in a microprocessor App 20050071614 - Jourdan, Stephan ; et al.	2005-03-31
Flag value renaming App 20050071518 - Samra, Nicholas G. ; et al.	2005-03-31
Computer with dynamic instruction reuse Grant 5,845,103 - Sodani , et al. December 1, 1	1998-12-01

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