So; Byung Se

Patent Applications and Registrations

Patent applications and USPTO patent grants for So; Byung Se.The latest application filed is for "semiconductor device for managing user data according to security level and method of operating the same".

Company Profile

0.40.43

So; Byung Se - Seoul KR
So; Byung-Se - Sungnam-si KR
So; Byung-Se - Gyeonggi-do KR
So; Byung-Se - Seongnam KR
So; Byung-Se - Seongnam-Si KR
SO; Byung-Se - Seongnam- City KR
So; Byung-se - Kyungki-do KR
So; Byung-se - Sungnam KR
So, Byung-Se - Sunae-dong KR
So, Byung-se - Sungnam-city KR
So; Byung-Se - Seongnam-shi KR
So; Byung Se - Bundanggu KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System on chip (SoC) capable of sharing resources with network device and devices having the SoC Grant 10,313,217 - Kim , et al.	2019-06-04
Semiconductor Device For Managing User Data According To Security Level And Method Of Operating The Same App 20160337322 - KANG; BO GYEONG ; et al.	2016-11-17
Semiconductor Device For Controlling Access Right To Resource Based On Pairing Technique And Method Thereof App 20160323283 - KANG; BO GYEONG ; et al.	2016-11-03
System On Chip (soc) And Devices Having The Soc App 20160269259 - KIM; Jin Min ; et al.	2016-09-15
Method of testing a memory module and hub of the memory module Grant 8,051,343 - Shin , et al. November 1, 2	2011-11-01
Method of testing a memory module and hub of the memory module App 20110113296 - Shin; Seung-Man ; et al.	2011-05-12
Determining operation mode for semiconductor memory device Grant 7,930,465 - Kim , et al. April 19, 2	2011-04-19
Multi-chip package for reducing parasitic load of pin Grant 7,868,438 - So , et al. January 11, 2	2011-01-11
Method of testing a memory module and hub of the memory module Grant 7,849,373 - Shin , et al. December 7, 2	2010-12-07
Multi-chip package for reducing parasitic load of pin Grant 7,847,383 - So , et al. December 7, 2	2010-12-07
Memory module with registers Grant 7,818,488 - Park , et al. October 19, 2	2010-10-19
Apparatus and method for testing circuit characteristics by using eye mask Grant 7,656,181 - Kim , et al. February 2, 2	2010-02-02
Memory module with stacked semiconductor devices Grant 7,615,869 - Koo , et al. November 10, 2	2009-11-10
Memory module, memory unit, and hub with non-periodic clock and methods of using the same Grant 7,606,110 - Han , et al. October 20, 2	2009-10-20
Multi-chip package for reducing parasitic load of pin Grant 7,566,958 - So , et al. July 28, 2	2009-07-28
Memory module test system for memory module including hub Grant 7,539,910 - Ahn , et al. May 26, 2	2009-05-26
Multi-chip Package For Reducing Parasitic Load Of Pin App 20090079496 - SO; Byung-Se ; et al.	2009-03-26
Data transmission system and method Grant 7,505,521 - Cho , et al. March 17, 2	2009-03-17
Method of testing a memory module and hub of the memory module App 20090044062 - Shin; Seung-Man ; et al.	2009-02-12
Method of testing a memory module and hub of the memory module Grant 7,447,954 - Shin , et al. November 4, 2	2008-11-04
Buffered memory module and method for testing same Grant 7,350,120 - Cho , et al. March 25, 2	2008-03-25
Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller Grant 7,334,137 - Jung , et al. February 19, 2	2008-02-19
Memory system having stub bus configuration Grant 7,313,715 - Yoo , et al. December 25, 2	2007-12-25
Multi-chip package for reducing parasitic load of pin App 20070228546 - So; Byung-Se ; et al.	2007-10-04
Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted Grant 7,276,786 - Cho , et al. October 2, 2	2007-10-02
Memory system having memory modules with different memory device loads Grant 7,254,675 - Lee , et al. August 7, 2	2007-08-07
Mounting structure in integrated circuit module Grant 7,227,258 - Cho , et al. June 5, 2	2007-06-05
Memory module and method of testing the same Grant 7,219,274 - Lee , et al. May 15, 2	2007-05-15
Semiconductor memory system having multiple system data buses Grant 7,215,561 - Park , et al. May 8, 2	2007-05-08
Multi-chip package for reducing parasitic load of pin App 20070040280 - So; Byung-Se ; et al.	2007-02-22
Memory module system with efficient control of on-die termination Grant 7,180,327 - So , et al. February 20, 2	2007-02-20
Circuit Board And Method For Manufacturing The Same App 20070033457 - PARK; Sung-Joo ; et al.	2007-02-08
Apparatus and method for testing circuit characteristics by using eye mask App 20070018637 - Kim; Woo-Seop ; et al.	2007-01-25
Memory module with stacked semiconductor devices App 20070018299 - Koo; Chang-Woo ; et al.	2007-01-25
Multi-chip package for reducing parasitic load of pin Grant 7,148,563 - So , et al. December 12, 2	2006-12-12
Memory module and a method of arranging a signal line of the same Grant 7,106,613 - Yoon , et al. September 12, 2	2006-09-12
Memory module Grant 7,072,201 - So , et al. July 4, 2	2006-07-04
Signal transmission circuits that use multiple input signals to generate a respective transmit signal Grant 7,049,849 - So , et al. May 23, 2	2006-05-23
Determining operation mode for semiconductor memory device App 20060098513 - Kim; Seok-Il ; et al.	2006-05-11
Error detecting memory module and method App 20060069948 - Seo; Jong-Cheol ; et al.	2006-03-30
Method of testing memory module and memory module App 20060064611 - Shin; Seung-Man ; et al.	2006-03-23
Memory module with memory devices of different capacity App 20060059298 - Cho; Jeong-Hyeon ; et al.	2006-03-16
Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted App 20060055017 - Cho; Jeong-Hyeon ; et al.	2006-03-16
Memory module, memory unit, and hub with non-periodic clock and methods of using the same App 20060044927 - Han; You-Keun ; et al.	2006-03-02
Memory module with improved data bus performance Grant 6,990,543 - Park , et al. January 24, 2	2006-01-24
Method of testing a memory module and hub of the memory module App 20060006419 - Shin; Seung-Man ; et al.	2006-01-12
Memory module system with efficient control of on-die termination App 20050212551 - So, Byung-Se ; et al.	2005-09-29
Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode Grant 6,944,737 - Ahn , et al. September 13, 2	2005-09-13
Memory module and a method of arranging a signal line of the same App 20050185439 - Yoon, Chil-Nam ; et al.	2005-08-25
Mounting structure in integrated circuit module App 20050104206 - Cho, Jeong-Hyeon ; et al.	2005-05-19
Memory module with registers App 20050097264 - Park, Kwang-Soo ; et al.	2005-05-05
Data transmission system and method App 20050089106 - Cho, Jeong-Hyeon ; et al.	2005-04-28
System board Grant 6,870,742 - Park , et al. March 22, 2	2005-03-22
Memory module App 20050036350 - So, Byung-se ; et al.	2005-02-17
Memory module test system App 20050023560 - Ahn, Young-Man ; et al.	2005-02-03
Memory module and method of testing the same App 20050010841 - Lee, Jung-Bae ; et al.	2005-01-13
Memory system with improved signal integrity App 20050002241 - Park, Sung-Joo ; et al.	2005-01-06
Buffered memory module and method for testing same App 20040264269 - Cho, Jeong-Hyeon ; et al.	2004-12-30
Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same Grant 6,836,138 - Park , et al. December 28, 2	2004-12-28
Module Having Test Architecture For Facilitating The Testing Of Ball Grid Array Packages, And Test Method Using The Same App 20040257103 - Park, Sung-Joo ; et al.	2004-12-23
Memory module with improved data bus performance App 20040260859 - Park, Myun-joo ; et al.	2004-12-23
High-speed memory system Grant 6,828,819 - Park , et al. December 7, 2	2004-12-07
Chip scale package, printed circuit board, and method of designing a printed circuit board Grant 6,815,621 - Park , et al. November 9, 2	2004-11-09
Signal transmission circuits that use multiple input signals to generate a respective transmit signal App 20040170131 - So, Byung-se ; et al.	2004-09-02
Memory module with improved data bus performance Grant 6,772,262 - Park , et al. August 3, 2	2004-08-03
Multi-chip package for reducing parasitic load of pin App 20040120176 - So, Byung-Se ; et al.	2004-06-24
Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices Grant 6,754,112 - Ahn , et al. June 22, 2	2004-06-22
Signal transmission circuits that use multiple input signals to generate a respective transmit signal and methods of operating the same Grant 6,714,595 - So , et al. March 30, 2	2004-03-30
Semiconductor memory system having multiple system data buses App 20040037133 - Park, Myun-Joo ; et al.	2004-02-26
Memory system having memory modules with different memory device loads App 20040024966 - Lee, Jae-Jun ; et al.	2004-02-05
Memory modules and packages using different orientations and terminal assignments Grant 6,632,705 - Kang , et al. October 14, 2	2003-10-14
High-speed memory system App 20030161196 - Park, Myun-Joo ; et al.	2003-08-28
System board App 20030039105 - Park, Myun-Joo ; et al.	2003-02-27
Memory modules having integral terminating resistors and computer system boards for use with same Grant 6,480,409 - Park , et al. November 12, 2	2002-11-12
Memory system having stub bus configuration App 20020161968 - Yoo, Chang-Sik ; et al.	2002-10-31
Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode App 20020135394 - Ahn, Young-man ; et al.	2002-09-26
Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices and methods of operating same App 20020114195 - Ahn, Young-Man ; et al.	2002-08-22
Two channel memory system having shared control and address bus and memory modules used therefor Grant 6,414,904 - So , et al. July 2, 2	2002-07-02
Socket for mounting memory module boards on a printed circuit board Grant 6,382,986 - Kim , et al. May 7, 2	2002-05-07
Chip scale package, printed circuit board, and method of designing a piinted circuit board App 20020038724 - Park, Myun Joo ; et al.	2002-04-04
Two channel memory system having shared control and address bus and memory modules used therefor App 20020001214 - So, Byung-Se ; et al.	2002-01-03
Memory modules having integral terminating resistors and computer system boards for use with same App 20010050858 - Park, Myun-joo ; et al.	2001-12-13
Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller App 20010042216 - Jung, Tae-Sung ; et al.	2001-11-15

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.