| Patent | Date |
|---|
Operand pool instruction reservation clustering in a scheduler circuit in a processor
Grant 11,392,410 - Priyadarshi , et al. July 19, 2 | 2022-07-19 |
Reach-based explicit dataflow processors, and related computer-readable media and methods
Grant 11,392,537 - Gupta , et al. July 19, 2 | 2022-07-19 |
Obsoleting Values Stored In Registers In A Processor Based On Processing Obsolescent Register-encoded Instructions
App 20220066779 - SARTORIUS; Thomas Andrew ; et al. | 2022-03-03 |
Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions
Grant 11,188,334 - Sartorius , et al. November 30, 2 | 2021-11-30 |
Operand Pool Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210318905 - PRIYADARSHI; Shivam ; et al. | 2021-10-14 |
Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)
Grant 11,113,068 - Tekmen , et al. September 7, 2 | 2021-09-07 |
Reach Matrix Scheduler Circuit For Scheduling Of Instructions To Be Executed In A Processor
App 20210216327 - TEKMEN; Yusuf Cagatay ; et al. | 2021-07-15 |
Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor
Grant 11,061,677 - Seth , et al. July 13, 2 | 2021-07-13 |
Systems and methods for processing instructions having wide immediate operands
Grant 11,036,512 - Perais , et al. June 15, 2 | 2021-06-15 |
Obsoleting Values Stored In Registers In A Processor Based On Processing Obsolescent Register-encoded Instructions
App 20210165658 - SARTORIUS; Thomas Andrew ; et al. | 2021-06-03 |
Latency-based instruction reservation station clustering in a scheduler circuit in a processor
Grant 11,023,243 - Tekmen , et al. June 1, 2 | 2021-06-01 |
Systems And Methods For Processing Instructions Having Wide Immediate Operands
App 20210089308 - PERAIS; Arthur ; et al. | 2021-03-25 |
Operand-based reach explicit dataflow processors, and related methods and computer-readable media
Grant 10,956,162 - Clancy , et al. March 23, 2 | 2021-03-23 |
Latency-based Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210026639 - TEKMEN; Yusuf Cagatay ; et al. | 2021-01-28 |
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices
Grant 10,896,041 - Priyadarshi , et al. January 19, 2 | 2021-01-19 |
Operand-based Reach Explicit Dataflow Processors, And Related Methods And Computer-readable Media
App 20200409712 - CLANCY; Robert Douglas ; et al. | 2020-12-31 |
Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor
Grant 10,877,768 - Priyadarshi , et al. December 29, 2 | 2020-12-29 |
Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture
Grant 10,860,328 - Priyadarshi , et al. December 8, 2 | 2020-12-08 |
Reach-based Explicit Dataflow Processors, And Related Computer-readable Media And Methods
App 20200301877 - GUPTA; Gagan ; et al. | 2020-09-24 |
Providing Late Physical Register Allocation And Early Physical Register Release In Out-of-order Processor (oop)-based Devices Im
App 20200097296 - Priyadarshi; Shivam ; et al. | 2020-03-26 |
Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase
Grant 10,551,896 - Priyadarshi , et al. Fe | 2020-02-04 |
Combining Load Or Store Instructions
App 20200004550 - THAKKER; Harsh ; et al. | 2020-01-02 |
Method, Apparatus, And System For Reducing Live Readiness Calculations In Reservation Stations
App 20190332385 - SMITH; Rodney Wayne ; et al. | 2019-10-31 |
Providing Early Pipeline Optimization Of Conditional Instructions In Processor-based Systems
App 20190294443 - Navada; Sandeep Suresh ; et al. | 2019-09-26 |
Fast Pipeline Restart In Processor With Decoupled Fetcher
App 20190155608 - PERAIS; Arthur ; et al. | 2019-05-23 |
Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor
Grant 10,108,417 - Krishna , et al. October 23, 2 | 2018-10-23 |
Method And Apparatus For Dynamic Clock And Voltage Scaling In A Computer Processor Based On Program Phase
App 20180074568 - PRIYADARSHI; Shivam ; et al. | 2018-03-15 |
Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase
Grant 9,851,774 - Priyadarshi , et al. December 26, 2 | 2017-12-26 |
Optimizing performance for context-dependent instructions
Grant 9,823,929 - Streett , et al. November 21, 2 | 2017-11-21 |
Write-allocation For A Cache Based On Execute Permissions
App 20170255569 - SARTORIUS; Thomas Andrew ; et al. | 2017-09-07 |
Method And Apparatus For Dynamic Clock And Voltage Scaling In A Computer Processor Based On Program Phase
App 20170192484 - Priyadarshi; Shivam ; et al. | 2017-07-06 |
Method And Apparatus For Effective Clock Scaling At Exposed Cache Stalls
App 20170090508 - PRIYADARSHI; Shivam ; et al. | 2017-03-30 |
Hierarchical Register File System
App 20170060593 - KRISHNA; Anil ; et al. | 2017-03-02 |
Efficient Handling Of Register Files
App 20170046160 - SETH; Kiran Ravi ; et al. | 2017-02-16 |
High Performance Recovery From Misspeculation Of Load Latency
App 20170046164 - MADHAVAN; Raghavan ; et al. | 2017-02-16 |
Storing Narrow Produced Values For Instruction Operands Directly In A Register Map In An Out-of-order Processor
App 20170046154 - Krishna; Anil ; et al. | 2017-02-16 |
Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media
Grant 9,477,476 - Brown , et al. October 25, 2 | 2016-10-25 |
Method and apparatus for selective renaming in a microprocessor
Grant 9,471,325 - Krishna , et al. October 18, 2 | 2016-10-18 |
Method to improve speed of executing return branch instructions in a processor
Grant 9,411,590 - Smith , et al. August 9, 2 | 2016-08-09 |
Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media
Grant 9,195,466 - Brown , et al. November 24, 2 | 2015-11-24 |
Physical Register Scrubbing In A Computer Microprocessor
App 20150268959 - KRISHNA; Anil ; et al. | 2015-09-24 |
Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information
Grant 8,943,300 - Stempel , et al. January 27, 2 | 2015-01-27 |
Method And Apparatus For Selective Renaming In A Microprocessor
App 20150019843 - KRISHNA; Anil ; et al. | 2015-01-15 |
Predecode repair cache for instructions that cross an instruction cache line
Grant 8,898,437 - Smith , et al. November 25, 2 | 2014-11-25 |
Method And Apparatus For Forwarding Literal Generated Data To Dependent Instructions More Efficiently Using A Constant Cache
App 20140281391 - Dieffenderfer; James Norris ; et al. | 2014-09-18 |
Optimizing Performance For Context-dependent Instructions
App 20140281405 - Streett; Daren Eugene ; et al. | 2014-09-18 |
Method To Improve Speed Of Executing Return Branch Instructions In A Processor
App 20140281394 - Smith; Rodney Wayne ; et al. | 2014-09-18 |
Fusing Immediate Value, Write-Based Instructions in Instruction Processing Circuits, and Related Processor Systems, Methods, and Computer-Readable Media
App 20140149722 - Brown; Melinda J. ; et al. | 2014-05-29 |
Power efficient instruction prefetch mechanism
Grant 8,661,229 - Sartorius , et al. February 25, 2 | 2014-02-25 |
Fusing Flag-producing And Flag-consuming Instructions In Instruction Processing Circuits, And Related Processor Systems, Methods, And Computer-readable Media
App 20140047221 - Irwin; Andrew S. ; et al. | 2014-02-13 |
Fusing Conditional Write Instructions Having Opposite Conditions In Instruction Processing Circuits, And Related Processor Systems, Methods, And Computer-readable Media
App 20130311754 - Brown; Melinda J. ; et al. | 2013-11-21 |
Link stack repair of erroneous speculative update
Grant 8,438,372 - Dieffenderfer , et al. May 7, 2 | 2013-05-07 |
Link stack repair of erroneous speculative update
Grant 8,438,371 - Dieffenderfer , et al. May 7, 2 | 2013-05-07 |
Debug circuit comparing processor instruction set operating mode
Grant 8,352,713 - Burke , et al. January 8, 2 | 2013-01-08 |
Selective powering of a BHT in a processor having variable length instructions
Grant 8,185,725 - Stempel , et al. May 22, 2 | 2012-05-22 |
Preloading instructions from an instruction set other than a currently executing instruction set
Grant 8,145,883 - Sartorius , et al. March 27, 2 | 2012-03-27 |
Link Stack Repair of Erroneous Speculative Update
App 20110320790 - Dieffenderfer; James Norris ; et al. | 2011-12-29 |
Methods and system for resolving simultaneous predicted branch instructions
Grant 8,082,428 - Smith , et al. December 20, 2 | 2011-12-20 |
Link Stack Repair of Erroneous Speculative Update
App 20110219220 - Dieffenderfer; James Norris ; et al. | 2011-09-08 |
System and method for using a working global history register
Grant 7,984,279 - Stempel , et al. July 19, 2 | 2011-07-19 |
Link stack repair of erroneous speculative update
Grant 7,971,044 - Dieffenderfer , et al. June 28, 2 | 2011-06-28 |
Pre-decoding variable length instructions
Grant 7,962,725 - Smith , et al. June 14, 2 | 2011-06-14 |
Method and apparatus for prefetching non-sequential instruction addresses
Grant 7,917,731 - Stempel , et al. March 29, 2 | 2011-03-29 |
Sliding-window, block-based branch target address cache
Grant 7,827,392 - Smith , et al. November 2, 2 | 2010-11-02 |
Caching memory attribute indicators with cached memory data field
Grant 7,805,588 - Bridges , et al. September 28, 2 | 2010-09-28 |
Virtually-tagged instruction cache with physically-tagged behavior
Grant 7,802,055 - Sartorius , et al. September 21, 2 | 2010-09-21 |
Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction
Grant 7,793,079 - Badran-Louca , et al. September 7, 2 | 2010-09-07 |
Caching instructions for a multiple-state processor
Grant 7,769,983 - Smith , et al. August 3, 2 | 2010-08-03 |
Preloading Instructions from an Instruction Set Other than a Currently Executing Instruction Set
App 20100169615 - Sartorius; Thomas Andrew ; et al. | 2010-07-01 |
Effective use of a BHT in processor having variable length instruction set execution modes
Grant 7,716,460 - Stempel , et al. May 11, 2 | 2010-05-11 |
System, method and software to preload instructions from an instruction set other than one currently executing
Grant 7,711,927 - Sartorius , et al. May 4, 2 | 2010-05-04 |
Efficient interrupt return address save mechanism
Grant 7,681,022 - Sartorius , et al. March 16, 2 | 2010-03-16 |
System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding
Grant 7,676,659 - Stempel , et al. March 9, 2 | 2010-03-09 |
Effective Use of a BHT in Processor Having Variable Length Instruction Set Execution Modes
App 20100058032 - Stempel; Brian Michael ; et al. | 2010-03-04 |
Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction
Grant 7,669,039 - McIlvaine , et al. February 23, 2 | 2010-02-23 |
Methods and System for Resolving Simultaneous Predicted Branch Instructions
App 20100023696 - Smith; Rodney Wayne ; et al. | 2010-01-28 |
Method and apparatus for managing cache partitioning using a dynamic boundary
Grant 7,650,466 - Stempel , et al. January 19, 2 | 2010-01-19 |
System and method wherein conditional instructions unconditionally provide output
Grant 7,624,256 - Sartorius , et al. November 24, 2 | 2009-11-24 |
Segmented pipeline flushing for mispredicted branches
Grant 7,624,254 - Smith , et al. November 24, 2 | 2009-11-24 |
Methods and system for resolving simultaneous predicted branch instructions
Grant 7,617,387 - Smith , et al. November 10, 2 | 2009-11-10 |
Power efficient instruction prefetch mechanism
Grant 7,587,580 - Sartorius , et al. September 8, 2 | 2009-09-08 |
Power Efficient Instruction Prefetch Mechanism
App 20090210663 - Sartorius; Thomas Andrew ; et al. | 2009-08-20 |
Instruction cache having fixed number of variable length instructions
Grant 7,568,070 - Bridges , et al. July 28, 2 | 2009-07-28 |
Predecode Repair Cache For Instructions That Cross An Instruction Cache Line
App 20090119485 - Smith; Rodney Wayne ; et al. | 2009-05-07 |
Link Stack Repair of Erroneous Speculative Update
App 20090094444 - Dieffenderfer; James Norris ; et al. | 2009-04-09 |
Apparatus for generating return address predictions for implicit and explicit subroutine calls
Grant 7,478,228 - Stempel , et al. January 13, 2 | 2009-01-13 |
Method and System for Expanding a Conditional Instruction into a Unconditional Instruction and a Select Instruction
App 20090006811 - Badran-Louca; Serena ; et al. | 2009-01-01 |
Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call
App 20080288753 - Stempel; Brian Michael ; et al. | 2008-11-20 |
System, Method and Software to Preload Instructions from a Variable-Length Instruction Set with Proper Pre-Decoding
App 20080250229 - Stempel; Brian Michael ; et al. | 2008-10-09 |
System, Method And Software To Preload Instructions From An Instruction Set Other Than One Currently Executing
App 20080229069 - Sartorius; Thomas Andrew ; et al. | 2008-09-18 |
Two-level interrupt service routine
Grant 7,424,563 - Birenbach , et al. September 9, 2 | 2008-09-09 |
Power saving methods and apparatus to selectively enable cache bits based on known processor state
Grant 7,421,568 - Stempel , et al. September 2, 2 | 2008-09-02 |
Pre-decode error handling via branch correction
Grant 7,415,638 - Smith , et al. August 19, 2 | 2008-08-19 |
Speculative Instruction Issue in a Simultaneously Multithreaded Processor
App 20080189521 - Augsburg; Victor Roberts ; et al. | 2008-08-07 |
Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions
Grant 7,406,613 - Dieffenderfer , et al. July 29, 2 | 2008-07-29 |
Segmented Pipeline Flushing for Mispredicted Branches
App 20080177992 - Smith; Rodney Wayne ; et al. | 2008-07-24 |
Use of Register Renaming System for Forwarding Intermediate Results Between Constituent Instructions of an Expanded Instruction
App 20080177987 - McIlvaine; Michael Scott ; et al. | 2008-07-24 |
Handling cache miss in an instruction crossing a cache line boundary
Grant 7,404,042 - Stempel , et al. July 22, 2 | 2008-07-22 |
Methods and apparatus to insure correct predecode
Grant 7,376,815 - Smith , et al. May 20, 2 | 2008-05-20 |
System and method for using a working global history register
App 20080109644 - Stempel; Brian Michael ; et al. | 2008-05-08 |
Speculative instruction issue in a simultaneously multithreaded processor
Grant 7,366,877 - Augsburg , et al. April 29, 2 | 2008-04-29 |
Effective Use of a BHT in Processor Having Variable Length Instruction Set Execution Modes
App 20080082807 - Stempel; Brian Michael ; et al. | 2008-04-03 |
Methods and System for Resolving Simultaneous Predicted Branch Instructions
App 20080077781 - Smith; Rodney Wayne ; et al. | 2008-03-27 |
Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call
App 20080059780 - Stempel; Brian Michael ; et al. | 2008-03-06 |
Debug Circuit Comparing Processor Instruction Set Operating Mode
App 20080040587 - Burke; Kevin Charles ; et al. | 2008-02-14 |
Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set
App 20080040576 - Stempel; Brian Michael ; et al. | 2008-02-14 |
Method and Apparatus for Prefetching Non-Sequential Instruction Addresses
App 20080034187 - Stempel; Brian Michael ; et al. | 2008-02-07 |
Efficient Interrupt Return Address Save Mechanism
App 20080028194 - Sartorius; Thomas Andrew ; et al. | 2008-01-31 |
Sliding-Window, Block-Based Branch Target Address Cache
App 20070283134 - Smith; Rodney Wayne ; et al. | 2007-12-06 |
Block-based Branch Target Address Cache
App 20070266228 - Smith; Rodney Wayne ; et al. | 2007-11-15 |
Pre-decoding Variable Length Instructions
App 20070260854 - Smith; Rodney Wayne ; et al. | 2007-11-08 |
Virtually-Tagged Instruction Cache with Physically-Tagged Behavior
App 20070250666 - Sartorius; Thomas Andrew ; et al. | 2007-10-25 |
Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions
Grant 7,278,012 - Sartorius , et al. October 2, 2 | 2007-10-02 |
Two-level interrupt service routine
App 20070204087 - Birenbach; Michael Egnoah ; et al. | 2007-08-30 |
Method and apparatus for repairing a link stack
App 20070204142 - Dieffenderfer; James Norris ; et al. | 2007-08-30 |
Caching memory attribute indicators with cached memory data field
App 20070094475 - Bridges; Jeffrey Todd ; et al. | 2007-04-26 |
Conditional instruction execution via emissary instruction for condition evaluation
Grant 7,210,024 - McIlvaine , et al. April 24, 2 | 2007-04-24 |
Method and apparatus for managing a return stack
Grant 7,203,826 - Smith , et al. April 10, 2 | 2007-04-10 |
Method and apparatus for managing cache partitioning
App 20070067574 - Stempel; Brian Michael ; et al. | 2007-03-22 |
Instruction cache having fixed number of variable length instructions
App 20070028050 - Bridges; Jeffrey Todd ; et al. | 2007-02-01 |
Method and apparatus for managing a link return stack
App 20060294346 - Stempel; Brian Michael ; et al. | 2006-12-28 |
Method and apparatus for predicting branch instructions
App 20060277397 - Sartorius; Thomas Andrew ; et al. | 2006-12-07 |
Handling cache miss in an instruction crossing a cache line boundary
App 20060265572 - Stempel; Brian Michael ; et al. | 2006-11-23 |
Caching instructions for a multiple-state processor
App 20060265573 - Smith; Rodney Wayne ; et al. | 2006-11-23 |
System and method wherein conditional instructions unconditionally provide output
App 20060236078 - Sartorius; Thomas Andrew ; et al. | 2006-10-19 |
Branch target address cache storing two or more branch target addresses per index
App 20060218385 - Smith; Rodney Wayne ; et al. | 2006-09-28 |
Forward looking branch target address caching
App 20060200655 - Smith; Rodney Wayne ; et al. | 2006-09-07 |
Power saving methods and apparatus to selectively enable cache bits based on known processor state
App 20060200686 - Stempel; Brian Michael ; et al. | 2006-09-07 |
Methods and apparatus to insure correct predecode
App 20060195830 - Smith; Rodney Wayne ; et al. | 2006-08-31 |
Method and apparatus for managing a return stack
App 20060190711 - Smith; Rodney Wayne ; et al. | 2006-08-24 |
Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes
Grant 7,093,100 - Bridges , et al. August 15, 2 | 2006-08-15 |
Conditional instruction execution via emissary instruction for condition evaluation
App 20060179288 - McIlvaine; Michael Scott ; et al. | 2006-08-10 |
Power efficient instruction prefetch mechanism
App 20060174090 - Sartorius; Thomas Andrew ; et al. | 2006-08-03 |
Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions
App 20060149981 - Dieffenderfer; James Norris ; et al. | 2006-07-06 |
Pre-decode error handling via branch correction
App 20060123326 - Smith; Rodney Wayne ; et al. | 2006-06-08 |
Efficiently calculating a branch target address
Grant 6,948,053 - Augsburg , et al. September 20, 2 | 2005-09-20 |
Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes
App 20050108497 - Bridges, Jeffrey Todd ; et al. | 2005-05-19 |
Speculative instruction issue in a simultaneously multithreaded processor
App 20050060518 - Augsburg, Victor Roberts ; et al. | 2005-03-17 |
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
Grant 6,816,962 - Augsburg , et al. November 9, 2 | 2004-11-09 |
Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions
App 20030163670 - Augsburg, Victor Roberts ; et al. | 2003-08-28 |
Efficiently calculating a branch target address
App 20030163677 - Augsburg, Victor Roberts ; et al. | 2003-08-28 |
System and method for tracing program execution within a superscalar processor
Grant 6,513,134 - Augsburg , et al. January 28, 2 | 2003-01-28 |
| 