loadpatents
name:-0.0059061050415039
name:-0.0057439804077148
name:-0.00037789344787598
Smith; Jesse Daniel Patent Filings

Smith; Jesse Daniel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Smith; Jesse Daniel.The latest application filed is for "implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic".

Company Profile
0.5.5
  • Smith; Jesse Daniel - Rochester MN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic
Grant 7,925,950 - Christensen , et al. April 12, 2
2011-04-12
Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels
Grant 7,911,827 - Behrends , et al. March 22, 2
2011-03-22
Implementing enhanced LBIST testing of paths including arrays
Grant 7,844,869 - Bushard , et al. November 30, 2
2010-11-30
Implementing Enhanced Array Access Time Tracking With Logic Built in Self Test of Dynamic Memory and Random Logic
App 20100218055 - Christensen; Todd Alan ;   et al.
2010-08-26
Implementing Enhanced SRAM Stability and Enhanced Chip Yield With Configurable Wordline Voltage Levels
App 20100188886 - Behrends; Derick Gardner ;   et al.
2010-07-29
Low power level shifting latch circuits with gated feedback for high speed integrated circuits
Grant 7,737,757 - Behrends , et al. June 15, 2
2010-06-15
Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability
Grant 7,724,585 - Behrends , et al. May 25, 2
2010-05-25
Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability
App 20100046277 - Behrends; Derick Gardner ;   et al.
2010-02-25
Low Power Level Shifting Latch Circuits With Gated Feedback for High Speed Integrated Circuits
App 20100019824 - Behrends; Derick Gardner ;   et al.
2010-01-28
Method and circuit for implementing enhanced LBIST testing of paths including arrays
App 20090183044 - Bushard; Louis Bernard ;   et al.
2009-07-16

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