Smith; Jack Robert
Patent Applications and Registrations
Patent applications and USPTO patent grants for Smith; Jack Robert.The latest application filed is for "coding of fpga and standard cell logic in a tiling structure".
- Smith; Jack Robert - South Burlington VT
| Patent | Date |
|---|---|
| System for expanding a window of valid data Grant 7,529,962 - Berhanu , et al. May 5, 2 | 2009-05-05 |
| Coding of FPGA and standard cell logic in a tiling structure App 20060190908 - Bajuk; Stanislav Peter ; et al. | 2006-08-24 |
| Coding of FPGA and standard cell logic in a tiling structure Grant 7,080,344 - Bajuk , et al. July 18, 2 | 2006-07-18 |
| Coding Of Fpga And Standard Cell Logic In A Tiling Structure App 20040268288 - Bajuk, Stanislav Peter ; et al. | 2004-12-30 |
| Method and apparatus for reducing power consumption of a processing integrated circuit Grant 6,834,353 - Smith , et al. December 21, 2 | 2004-12-21 |
| Method and system for optimizing code using an optimizing coprocessor Grant 6,820,254 - Smith , et al. November 16, 2 | 2004-11-16 |
| Method and apparatus for reducing power comsumption of a processing integrated circuit App 20030079150 - Smith, Jack Robert ; et al. | 2003-04-24 |
| Method and system for optimizing code using an optimizing coprocessor App 20020147970 - Smith, Jack Robert ; et al. | 2002-10-10 |
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