loadpatents
name:-0.00049400329589844
name:-0.016778945922852
name:-0.20233392715454
Slob; Arie Patent Filings

Slob; Arie

Patent Applications and Registrations

Patent applications and USPTO patent grants for Slob; Arie.The latest application filed is for "integrated cmos circuit comprising a substrate bias voltage generator".

Company Profile
0.15.0
  • Slob; Arie - Eindhoven NL
  • Slob; Arie - Emmasingel Eindhoven NL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated CMOS circuit comprising a substrate bias voltage generator
Grant 4,820,936 - Veendrick , et al. April 11, 1
1989-04-11
Integrated injection logic circuits
Grant 4,714,842 - Hart , et al. * December 22, 1
1987-12-22
Series/parallel/series shift register memory comprising redundant parallel-connected storage registers, and display apparatus comprising a picture memory thus organized
Grant 4,563,752 - Pelgrom , et al. January 7, 1
1986-01-07
Method of manufacturing programmable semiconductor device
Grant 4,536,948 - Te Velde , et al. August 27, 1
1985-08-27
Programmable semiconductor device and method of manufacturing same
Grant 4,460,914 - te Velde , et al. July 17, 1
1984-07-17
Integrated injection logic circuits
Grant 4,286,177 - Hart , et al. August 25, 1
1981-08-25
Semiconductor device and method of manufacturing same
Grant 4,283,837 - Slob August 18, 1
1981-08-18
Semiconductor device having non-metallic connection zones
Grant 4,161,745 - Slob July 17, 1
1979-07-17
Memory array
Grant 4,122,542 - Camerik , et al. October 24, 1
1978-10-24
Linear amplifier circuit with integrated current injector
Grant 4,078,208 - Hart , et al. March 7, 1
1978-03-07
Integrated injection logic memory circuit
Grant 4,056,810 - Hart , et al. November 1, 1
1977-11-01
Display device for a counting mechanism, such as a clock or watch
Grant 3,987,617 - Slob October 26, 1
1976-10-26
Method of manufacturing a semiconductor device utilizing simultaneous outdiffusion during epitaxial growth
Grant 3,930,909 - Schmitz , et al. January 6, 1
1976-01-06
Monolithic Ic With Complementary Transistors And Plural Buried Layers
Grant 3,702,428 - Schmitz , et al. November 7, 1
1972-11-07
Semiconductor Device With Complementary Transistors
Grant 3,617,827 - Schmitz , et al. November 2, 1
1971-11-02

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed