Slemmer; William C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Slemmer; William C..The latest application filed is for "rfid-based asset security and tracking system, apparatus and method".

Company Profile

0.17.3

Slemmer; William C. - Frisco TX
Slemmer; William C. - Dallas TX
Slemmer; William C. - Colorado Springs CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Rfid-based Asset Security And Tracking System, Apparatus And Method App 20130201337 - Tapp; Hollis M. ; et al.	2013-08-08
RFID-based asset security and tracking system, apparatus and method Grant 8,334,775 - Tapp , et al. December 18, 2	2012-12-18
Rfid-based Asset Security And Tracking System, Apparatus And Method App 20090322537 - Tapp; Hollis M. ; et al.	2009-12-31
Security And Surveillance System App 20090174772 - Tapp; Hollis M. ; et al.	2009-07-09
Semiconductor memory with power-on reset controlled latched row line repeaters Grant 5,526,318 - Slemmer , et al. June 11, 1	1996-06-11
Integrated circuit with fuse circuitry simulating fuse blowing Grant 5,517,455 - McClure , et al. May 14, 1	1996-05-14
Clock generator circuit with low current frequency divider Grant 5,469,116 - Slemmer November 21, 1	1995-11-21
Structure for deselecting broken select lines in memory arrays Grant 5,465,233 - Slemmer November 7, 1	1995-11-07
Precharging output driver circuit Grant 5,450,019 - McClure , et al. September 12, 1	1995-09-12
Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same Grant 5,440,516 - Slemmer August 8, 1	1995-08-08
Compensating delay element for clock generation in a memory device Grant 5,424,985 - McClure , et al. June 13, 1	1995-06-13
Output driver circuit with body bias control for multiple power supply operation Grant 5,422,591 - Rastegar , et al. June 6, 1	1995-06-06
Semiconductor memory with inverted write-back capability and method of testing a memory using inverted write-back Grant 5,396,464 - Slemmer March 7, 1	1995-03-07
Temperature-compensated voltage level sense circuit Grant 5,365,129 - Slemmer , et al. November 15, 1	1994-11-15
Semiconductor memory with sequenced latched row line repeaters Grant 5,124,951 - Slemmer , et al. June 23, 1	1992-06-23
Semiconductor memory with power-on reset controlled latched row line repeaters Grant 5,121,358 - Slemmer , et al. June 9, 1	1992-06-09
Semiconductor memory having latched repeaters for memory row line selection Grant 5,119,340 - Slemmer June 2, 1	1992-06-02
Semiconductor memory with a clocked access code for test mode entry Grant 5,072,137 - Slemmer December 10, 1	1991-12-10
Semiconductor memory with sequential clocked access codes for test mode entry Grant 5,072,138 - Slemmer , et al. December 10, 1	1991-12-10
Two-way regulated substrate bias generator Grant 4,403,158 - Slemmer September 6, 1	1983-09-06

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