Sivaraman; Mukund

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sivaraman; Mukund.The latest application filed is for "compilation flow for a heterogeneous multi-core architecture".

Company Profile

3.8.7

Sivaraman; Mukund - Palo Alto CA
Sivaraman; Mukund - Mountain View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Compilation flow for a heterogeneous multi-core architecture Grant 10,860,766 - Sivaraman , et al. December 8, 2	2020-12-08
Compilation Flow For A Heterogeneous Multi-core Architecture App 20200372200 - Sivaraman; Mukund ; et al.	2020-11-26
Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architecture Grant 10,628,622 - Sivaraman , et al.	2020-04-21
Design-for-testability (DFT) insertion at register-transfer-level (RTL) Grant 10,372,858 - Odiz , et al.	2019-08-06
Design-for-testability (dft) Insertion At Register-transfer-level (rtl) App 20180246996 - Odiz; Eyal ; et al.	2018-08-30
Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages Grant 7,484,079 - Gupta , et al. January 27, 2	2009-01-27
Method of using clock cycle-time in determining loop schedules during circuit design Grant 7,096,438 - Sivaraman , et al. August 22, 2	2006-08-22
System for and method of clock cycle-time analysis using mode-slicing mechanism Grant 7,000,137 - Sivaraman , et al. February 14, 2	2006-02-14
Method for designing minimal cost, timing correct hardware during circuit synthesis Grant 6,966,043 - Sivaraman , et al. November 15, 2	2005-11-15
Methods and apparatus for digital circuit design generation Grant 6,952,816 - Gupta , et al. October 4, 2	2005-10-04
System for and a method of controlling pipeline process stages App 20040088520 - Gupta, Shail Aditya ; et al.	2004-05-06
Digital circuit synthesis including timing convergence and routability App 20040068711 - Gupta, Shail-Aditya ; et al.	2004-04-08
Method for designing minimal cost, timing correct hardware during circuit synthesis App 20040068706 - Sivaraman, Mukund ; et al.	2004-04-08
System for and method of clock cycle-time analysis using mode-slicing mechanism App 20040068705 - Sivaraman, Mukund ; et al.	2004-04-08
Method of using clock cycle-time in determining loop schedules during circuit design App 20040068708 - Sivaraman, Mukund ; et al.	2004-04-08

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