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name:-0.0098187923431396
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Sitaram; Arkalgud Patent Filings

Sitaram; Arkalgud

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sitaram; Arkalgud.The latest application filed is for "protective elements for bonded structures".

Company Profile
1.8.14
  • Sitaram; Arkalgud - Cupertino CA
  • Sitaram; Arkalgud - Cedar Park TX
  • Sitaram; Arkalgud - Wappingers Falls TX
  • Sitaram; Arkalgud - Fishkill NY
  • Sitaram; Arkalgud - Erlangen DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Protective Elements For Bonded Structures
App 20200328162 - Haba; Belgacem ;   et al.
2020-10-15
Circuit assemblies with multiple interposer substrates, and methods of fabrication
Grant 9,905,507 - Shen , et al. February 27, 2
2018-02-27
Circuit Assemblies With Multiple Interposer Substrates, And Methods Of Fabrication
App 20160293534 - SHEN; Hong ;   et al.
2016-10-06
Integrated Circuit Assemblies With Reinforcement Frames, And Methods Of Manufacture
App 20160276294 - KATKAR; Rajesh ;   et al.
2016-09-22
Circuit assemblies with multiple interposer substrates, and methods of fabrication
Grant 9,402,312 - Shen , et al. July 26, 2
2016-07-26
Integrated circuit assemblies with reinforcement frames, and methods of manufacture
Grant 9,355,997 - Katkar , et al. May 31, 2
2016-05-31
Circuit Assemblies With Multiple Interposer Substrates, And Methods Of Fabrication
App 20150327367 - SHEN; Hong ;   et al.
2015-11-12
Integrated Circuit Assemblies With Reinforcement Frames, And Methods Of Manufacture
App 20150262972 - KATKAR; Rajesh ;   et al.
2015-09-17
Stacked semiconductor components
App 20080153200 - Sitaram; Arkalgud
2008-06-26
Semiconductor component with through-vias
App 20080142928 - Sitaram; Arkalgud ;   et al.
2008-06-19
Self-aligned through vias for chip stacking
App 20080116584 - Sitaram; Arkalgud
2008-05-22
Resistive memory cell configuration and method for sensing resistance values
Grant 7,068,533 - Ferrant , et al. June 27, 2
2006-06-27
Resistive Memory Cell Configuration And Method For Sensing Resistance Values
App 20060067103 - Ferrant; Richard ;   et al.
2006-03-30
Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure
Grant 6,958,501 - Sitaram , et al. October 25, 2
2005-10-25
Storage capacitor and associated contact-making structure and a method for fabricating the storage capacitor and the contact-making structure
Grant 6,844,581 - Sitaram , et al. January 18, 2
2005-01-18
Method for fabricating a memory cell
Grant 6,833,302 - Sitaram December 21, 2
2004-12-21
Method for fabricating a gate stack in very large scale integrated semiconductor memories
Grant 6,723,657 - Sitaram April 20, 2
2004-04-20
Method for fabricating a memory cell
App 20030162352 - Sitaram, Arkalgud
2003-08-28
Method for fabricating a gate stack in very large scale integrated semiconductor memories
App 20030036278 - Sitaram, Arkalgud
2003-02-20
Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure
App 20020115227 - Sitaram, Arkalgud ;   et al.
2002-08-22
Storage capacitor and associated contact-making structure and a method for fabricating the storage capacitor and the contact-making structure
App 20020066921 - Sitaram, Arkalgud ;   et al.
2002-06-06
Method for fabricating a ferroelectric or paraelectric metal oxide-containing layer and a memory component therefrom
App 20020061604 - Sitaram, Arkalgud ;   et al.
2002-05-23

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