Sisodia; Rajiv Kumar
Patent Applications and Registrations
Patent applications and USPTO patent grants for Sisodia; Rajiv Kumar.The latest application filed is for "memory architecture with dc biasing".
- Sisodia; Rajiv Kumar - Bangalore IN
| Patent | Date |
|---|---|
| Wordline coupling techniques Grant 11,430,506 - Sisodia , et al. August 30, 2 | 2022-08-30 |
| Memory Architecture with DC Biasing App 20220254411 - Chen; Andy Wangkun ; et al. | 2022-08-11 |
| Bitcell Architecture Using Buried Metal App 20220223514 - Sisodia; Rajiv Kumar ; et al. | 2022-07-14 |
| Power-gating techniques with buried metal Grant 11,322,197 - Sisodia , et al. May 3, 2 | 2022-05-03 |
| Techniques for powering memory Grant 11,315,628 - Sisodia , et al. April 26, 2 | 2022-04-26 |
| Power-Gating Techniques with Buried Metal App 20220122656 - Sisodia; Rajiv Kumar ; et al. | 2022-04-21 |
| Backside Power Supply Techniques App 20220123751 - Thyagarajan; Sriram ; et al. | 2022-04-21 |
| Techniques For Powering Memory App 20220122654 - Sisodia; Rajiv Kumar ; et al. | 2022-04-21 |
| Bitline precharging techniques Grant 11,100,965 - Sisodia , et al. August 24, 2 | 2021-08-24 |
| Wordline Coupling Techniques App 20210249070 - Sisodia; Rajiv Kumar ; et al. | 2021-08-12 |
| Tri-state buffering techniques Grant 11,074,945 - Sisodia , et al. July 27, 2 | 2021-07-27 |
| Memory with a controllable I/O functional unit Grant 10,861,575 - Sisodia , et al. December 8, 2 | 2020-12-08 |
| Providing a discharge boundary using bitline discharge control circuitry for an integrated circuit Grant 10,734,065 - Sisodia , et al. | 2020-08-04 |
| Memory with a Controllable I/O Functional Unit App 20200066365 - Sisodia; Rajiv Kumar ; et al. | 2020-02-27 |
| Memory with a controllable I/O functional unit Grant 10,460,822 - Sisodia , et al. Oc | 2019-10-29 |
| Bitline Discharge Control Circuitry App 20190066770 - Sisodia; Rajiv Kumar ; et al. | 2019-02-28 |
| Memory with a Controllable I/O Functional Unit App 20190066814 - Sisodia; Rajiv Kumar ; et al. | 2019-02-28 |
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