Sirinorakul; Saravuth

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sirinorakul; Saravuth.The latest application filed is for "flip chip semiconductor package with a leadframe to enhance package mechanical stability and heat dissipation".

Company Profile

15.94.49

Sirinorakul; Saravuth - Bangkok TH
Sirinorakul; Saravuth - Bagkok TH
Sirinorakul; Saravuth - Bangna TH

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Flip Chip Semiconductor Package With A Leadframe To Enhance Package Mechanical Stability And Heat Dissipation App 20220270942 - Charusabha; Nataporn ; et al.	2022-08-25
Semiconductor Device and Method of Forming Protective Layer Around Cavity of Semiconductor Die App 20220077019 - Sirinorakul; Saravuth ; et al.	2022-03-10
Semiconductor Packages With Integrated Shielding App 20220028798 - SIRINORAKUL; Saravuth ; et al.	2022-01-27
Stacked dies electrically connected to a package substrate by lead terminals Grant 11,227,818 - Lam , et al. January 18, 2	2022-01-18
Cavity wall structure for semiconductor packaging Grant 11,139,233 - Tan , et al. October 5, 2	2021-10-05
Semiconductor Packages And Methods Of Packaging Semiconductor Devices App 20210035891 - LAM; Wing Keung ; et al.	2021-02-04
Cavity Wall Structure For Semiconductor Packaging App 20200321273 - TAN; Hua Hong ; et al.	2020-10-08
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 10,734,247 - Sirinorakul , et al.	2020-08-04
Cavity wall structure for semiconductor packaging Grant 10,707,161 - Tan , et al.	2020-07-07
Semiconductor package with a heat spreader and method of manufacturing thereof Grant 10,658,277 - Dimaano, Jr. , et al.	2020-05-19
Semiconductor package with plated metal shielding and a method thereof Grant 10,600,741 - Yenrudee , et al.	2020-03-24
Conductive shield for semiconductor package Grant 10,586,771 - Sirinorakul , et al.	2020-03-10
Semiconductor package with partial plating on contact side surfaces Grant 10,515,878 - Nondhasitthichai , et al. Dec	2019-12-24
Semiconductor package with multiple stacked leadframes and a method of manufacturing the same Grant 10,361,146 - Sirinorakul , et al.	2019-07-23
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 10,325,782 - Sirinorakul , et al.	2019-06-18
Semiconductor Package With Multiple Stacked Leadframes And A Method Of Manufacturing The Same App 20190181077 - Sirinorakul; Saravuth ; et al.	2019-06-13
Semiconductor package with multiple stacked leadframes and a method of manufacturing the same Grant 10,276,477 - Sirinorakul , et al.	2019-04-30
Method of improving adhesion between molding compounds and an apparatus thereof Grant 10,269,686 - Yenrudee , et al.	2019-04-23
Semiconductor package with plated metal shielding and a method thereof Grant 10,242,953 - Yenrudee , et al.	2019-03-26
Semiconductor package with full plating on contact side surfaces and methods thereof Grant 10,242,934 - Sirinorakul	2019-03-26
Thermally Enhanced Leadless Semiconductor Package And Method Of Manufacturing Thereof App 20190051585 - DIMAANO JR.; Antonio Bambalan ; et al.	2019-02-14
Semiconductor package with partial plating on contact side surfaces Grant 10,204,850 - Nondhasitthichai , et al. Feb	2019-02-12
Cavity Wall Structure For Semiconductor Packaging App 20190043797 - TAN; Hua Hong ; et al.	2019-02-07
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 10,163,658 - Sirinorakul , et al. Dec	2018-12-25
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 10,096,490 - Sirinorakul , et al. October 9, 2	2018-10-09
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 10,032,645 - Sirinorakul , et al. July 24, 2	2018-07-24
Plated terminals with routing interconnections semiconductor device Grant 9,972,563 - Sirinorakul May 15, 2	2018-05-15
Flip chip cavity package Grant 9,947,605 - Sirinorakul , et al. April 17, 2	2018-04-17
Plated terminals with routing interconnections semiconductor device Grant 9,922,913 - Sirinorakul March 20, 2	2018-03-20
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 9,922,843 - Sirinorakul , et al. March 20, 2	2018-03-20
Plated terminals with routing interconnections semiconductor device Grant 9,922,914 - Sirinorakul March 20, 2	2018-03-20
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 9,917,038 - Sirinorakul , et al. March 13, 2	2018-03-13
Semiconductor Package With Multiple Molding Routing Layers And A Method Of Manufacturing The Same App 20180061667 - Sirinorakul; Saravuth ; et al.	2018-03-01
Molded leadframe substrate semiconductor package Grant 9,899,208 - Nondhasitthichai , et al. February 20, 2	2018-02-20
Semiconductor Package With Multiple Molding Routing Layers And A Method Of Manufacturing The Same App 20170352555 - Sirinorakul; Saravuth ; et al.	2017-12-07
Semiconductor Package With Multiple Molding Routing Layers And A Method Of Manufacturing The Same App 20170352610 - Sirinorakul; Saravuth ; et al.	2017-12-07
Semiconductor Package With Multiple Molding Routing Layers And A Method Of Manufacturing The Same App 20170352554 - Sirinorakul; Saravuth ; et al.	2017-12-07
Singulation method for semiconductor package with plating on side of connectors Grant 9,818,676 - Sirinorakul , et al. November 14, 2	2017-11-14
Semiconductor package with multiple molding routing layers and a method of manufacturing the same Grant 9,805,955 - Sirinorakul , et al. October 31, 2	2017-10-31
Semiconductor package with partial plating on contact side surfaces Grant 9,773,722 - Nondhasitthichai , et al. September 26, 2	2017-09-26
Flip chip cavity package Grant 9,761,435 - Sirinorakul , et al. September 12, 2	2017-09-12
Semiconductor package with partial plating on contact side surfaces Grant 9,741,642 - Nondhasitthichai , et al. August 22, 2	2017-08-22
Molded leadframe substrate semiconductor package Grant 9,711,343 - Nondhasitthichai , et al. July 18, 2	2017-07-18
Plated Terminals With Routing Interconnections Semiconductor Device App 20160300786 - Sirinorakul; Saravuth	2016-10-13
Plated Terminals With Routing Interconnections Semiconductor Device App 20160300783 - Sirinorakul; Saravuth	2016-10-13
Plated Terminals With Routing Interconnections Semiconductor Device App 20160293533 - Sirinorakul; Saravuth	2016-10-06
Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow Grant 9,449,900 - Sirinorakul , et al. September 20, 2	2016-09-20
Plated terminals with routing interconnections semiconductor device Grant 9,449,905 - Sirinorakul September 20, 2	2016-09-20
Singulation Method For Semiconductor Package With Plating On Side Of Connectors App 20160240460 - Sirinorakul; Saravuth ; et al.	2016-08-18
Post-mold for semiconductor package having exposed traces Grant 9,397,031 - Sirinorakul July 19, 2	2016-07-19
Post-mold For Semiconductor Package Having Exposed Traces App 20160172282 - Sirinorakul; Saravuth	2016-06-16
Auxiliary leadframe member for stabilizing the bond wire process Grant 9,355,940 - Sirinorakul May 31, 2	2016-05-31
Singulation method for semiconductor package with plating on side of connectors Grant 9,349,679 - Sirinorakul , et al. May 24, 2	2016-05-24
Semiconductor Package Having Routing Traces Therein App 20160064310 - Sirinorakul; Saravuth ; et al.	2016-03-03
Thermal leadless array package with die attach pad locking feature Grant 9,196,504 - Loh , et al. November 24, 2	2015-11-24
Molded leadframe substrate semiconductor package Grant 9,196,470 - Nondhasitthichai , et al. November 24, 2	2015-11-24
Method for forming lead frame land grid array Grant 9,099,317 - Nondhasitthichai , et al. August 4, 2	2015-08-04
Molded leadframe substrate semiconductor package Grant 9,099,294 - Nondhasitthichai , et al. August 4, 2	2015-08-04
Molded leadframe substrate semiconductor package Grant 9,093,486 - Nondhasitthichai , et al. July 28, 2	2015-07-28
Molded leadframe substrate semiconductor package Grant 9,082,607 - Nondhasitthichai , et al. July 14, 2	2015-07-14
Conductive Shield For Semiconductor Package App 20150171022 - Sirinorakul; Saravuth ; et al.	2015-06-18
Methods of manufacturing semiconductor devices including terminals with internal routing interconnections Grant 9,029,198 - Sirinorakul , et al. May 12, 2	2015-05-12
Post-mold for semiconductor package having exposed traces Grant 9,006,034 - Sirinorakul April 14, 2	2015-04-14
Protruding terminals with internal routing interconnections semiconductor device Grant 9,000,590 - Sirinorakul , et al. April 7, 2	2015-04-07
Apparatus for and methods of attaching heat slugs to package tops Grant 8,871,571 - Sirinorakul October 28, 2	2014-10-28
Flip-chip leadframe semiconductor package Grant 8,816,482 - Sirinorakul , et al. August 26, 2	2014-08-26
Leadframe based multi terminal IC package Grant 8,722,461 - Sirinorakul May 13, 2	2014-05-13
Very extremely thin semiconductor package Grant 8,704,381 - Nondhasitthichai , et al. April 22, 2	2014-04-22
Lead frame land grid array with routing connector trace under unit Grant 8,685,794 - Nondhasitthichai , et al. April 1, 2	2014-04-01
Lead frame ball grid array with traces under die Grant 8,652,879 - Nondhasitthichai , et al. February 18, 2	2014-02-18
Lead frame land grid array Grant 8,648,474 - Nondhasittichai , et al. February 11, 2	2014-02-11
Very Extremely Thin Semiconductor Package App 20140015117 - Nondhasitthichai; Somchai ; et al.	2014-01-16
Thermal Leadless Array Package With Die Attach Pad Locking Feature App 20140008777 - LOH; Albert ; et al.	2014-01-09
Lead Frame Land Grid Array With Routing Connector Trace Under Unit App 20130337609 - Nondhasitthichai; Somchai ; et al.	2013-12-19
Protruding Terminals With Internal Routing Interconnections Semiconductor Device App 20130299980 - Sirinorakul; Saravuth ; et al.	2013-11-14
Plated Terminals With Routing Interconnections Semiconductor Device App 20130299979 - Sirinorakul; Saravuth	2013-11-14
Methods Of Manufacturing Semiconductor Devices Including Terminals With Internal Routing Interconnections App 20130302944 - Sirinorakul; Saravuth ; et al.	2013-11-14
Very extremely thin semiconductor package Grant 8,575,762 - Nondhasitthichai , et al. November 5, 2	2013-11-05
Leadframe based multi terminal IC package Grant 8,575,732 - Sirinorakul November 5, 2	2013-11-05
Lead Frame Ball Grid Array With Traces Under Die App 20130280866 - Nondhasitthichai; Somchai ; et al.	2013-10-24
Molded Leadframe Substrate Semiconductor Package App 20130243893 - Nondhasitthichai; Somchai ; et al.	2013-09-19
Lead Frame Land Grid Array App 20130234307 - Nondhasittichai; Somchai ; et al.	2013-09-12
Leadframe Based Multi Terminal Ic Package App 20130210197 - Sirinorakul; Saravuth	2013-08-15
Lead frame ball grid array with traces under die Grant 8,492,906 - Nondhasitthichai , et al. July 23, 2	2013-07-23
Lead frame land grid array with routing connector trace under unit Grant 8,487,451 - Nondhasitthichai , et al. July 16, 2	2013-07-16
Lead frame ball grid array with traces under die having interlocking features Grant 8,460,970 - Sirinorakul June 11, 2	2013-06-11
Lead frame ball grid array with traces under die having interlocking features Grant 8,461,694 - Sirinorakul June 11, 2	2013-06-11
Auxiliary leadframe member for stabilizing the bond wire process Grant 8,368,189 - Sirinorakul February 5, 2	2013-02-05
Molded leadframe substrate semiconductor package Grant 8,338,922 - Sirinorakul , et al. December 25, 2	2012-12-25
Lead frame land grid array Grant 8,310,060 - Nondhasittichai , et al. November 13, 2	2012-11-13
Apparatus For And Methods Of Attaching Heat Slugs To Package Tops App 20120094438 - Sirinorakul; Saravuth	2012-04-19
Qfn Process For Strip Test App 20120066899 - Sirinorakul; Saravuth ; et al.	2012-03-22
Method of manufacturing semiconductor package containing flip-chip arrangement Grant 8,129,229 - Sirinorakul , et al. March 6, 2	2012-03-06
Singulation Method For Semiconductor Package With Plating On Side Of Connectors App 20120049335 - Sirinorakul; Saravuth ; et al.	2012-03-01
Package with heat transfer Grant 8,125,077 - Sirinorakul , et al. February 28, 2	2012-02-28
Method and apparatus for no lead semiconductor package Grant 8,071,426 - Sirinorakul , et al. December 6, 2	2011-12-06
Method and apparatus for no lead semiconductor package Grant 8,063,470 - Sirinorakul , et al. November 22, 2	2011-11-22
Apparatus For And Methods Of Attaching Heat Slugs To Package Tops App 20110241189 - Sirinorakul; Saravuth	2011-10-06
Leadframe Based Multi Terminal Ic Package App 20110221051 - Sirinorakul; Saravuth	2011-09-15
Package with heat transfer Grant 8,013,437 - Sirinorakul , et al. September 6, 2	2011-09-06
Lead Frame Ball Grid Array With Traces Under Die App 20110198752 - Nondhasitthichai; Somchai ; et al.	2011-08-18
Lead Frame Land Grid Array With Routing Connector Trace Under Unit App 20110147931 - Nondhasitthichai; Somchai ; et al.	2011-06-23
Auxiliary Leadframe Member For Stabilizing The Bond Wire Process App 20110133319 - Sirinorakul; Saravuth	2011-06-09
Molded Leadframe Substrate Semiconductor Package App 20110076805 - Nondhasitthichai; Somchai ; et al.	2011-03-31
Flip Chip Cavity Package App 20110039371 - Sirinorakul; Saravuth ; et al.	2011-02-17
Leadframe Feature To Minimize Flip-chip Semiconductor Die Collapse During Flip-chip Reflow App 20110018111 - Sirinorakul; Saravuth ; et al.	2011-01-27
Package With Heat Transfer App 20100327432 - Sirinorakul; Saravuth ; et al.	2010-12-30
Method And Apparatus For No Lead Semiconductor Package App 20100311208 - Sirinorakul; Saravuth ; et al.	2010-12-09
Molded leadframe substrate semiconductor package Grant 7,790,512 - Sirinorakul , et al. September 7, 2	2010-09-07
Very extremely thin semiconductor package App 20100127363 - Nondhasitthichai; Somchai ; et al.	2010-05-27
Lead frame land grid array App 20090209064 - Nonahasitthichai; Somchai ; et al.	2009-08-20
Flip-chip Leadframe Semiconductor Package App 20090146276 - SIRINORAKUL; Saravuth ; et al.	2009-06-11
Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound Grant 7,327,017 - Sirinorakul , et al. February 5, 2	2008-02-05
Process of fabricating semiconductor packages using leadframes roughened with chemical etchant Grant 7,205,180 - Sirinorakul , et al. April 17, 2	2007-04-17
Method of fabricating no-lead package for semiconductor die with half-etched leadframe Grant 7,153,724 - Sirinorakul , et al. December 26, 2	2006-12-26
Flat no-lead semiconductor die package including stud terminals Grant 7,060,535 - Sirinorakul , et al. June 13, 2	2006-06-13
Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound Grant 7,049,683 - Sirinorakul , et al. May 23, 2	2006-05-23
Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound App 20060097366 - Sirinorakul; Saravuth ; et al.	2006-05-11
Method of fabricating semiconductor chip package using screen printing of epoxy on wafer Grant 6,943,061 - Sirinorakul , et al. September 13, 2	2005-09-13

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