Sinharoy; Balaram

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sinharoy; Balaram.The latest application filed is for "providing a dynamic random-access memory cache as second type memory".

Company Profile

42.200.178

Sinharoy; Balaram - Poughkeepsie NY
Sinharoy; Balaram - Austin TX
Sinharoy; Balaram - Poughkeepise NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Ultra-low precision floating-point fused multiply-accumulate unit Grant 11,455,142 - Agrawal , et al. September 27, 2	2022-09-27
Instruction fusion after register rename Grant 11,256,509 - Silberman , et al. February 22, 2	2022-02-22
Providing a dynamic random-access memory cache as second type memory Grant 11,221,770 - Abali , et al. January 11, 2	2022-01-11
Coalescing global completion table entries in an out-of-order processor Grant 11,204,772 - Silberman , et al. December 21, 2	2021-12-21
Load-store unit with partitioned reorder queues with single cam port Grant 11,175,925 - Gonzalez , et al. November 16, 2	2021-11-16
Load-store unit with partitioned reorder queues with single cam port Grant 11,175,924 - Gonzalez , et al. November 16, 2	2021-11-16
Dynamic fusion based on operand size Grant 11,157,280 - Boersma , et al. October 26, 2	2021-10-26
Providing A Dynamic Random-access Memory Cache As Second Type Memory App 20210165580 - ABALI; Bulent ; et al.	2021-06-03
Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses Grant 10,977,047 - Lloyd , et al. April 13, 2	2021-04-13
Handling effective address synonyms in a load-store unit that operates without address translation Grant 10,963,248 - Lloyd , et al. March 30, 2	2021-03-30
Head and tail pointer manipulation in a first-in-first-out issue queue Grant 10,942,747 - Karve , et al. March 9, 2	2021-03-09
Scalable dependency matrix with a single summary bit in an out-of-order processor Grant 10,929,140 - Silberman , et al. February 23, 2	2021-02-23
Block based allocation and deallocation of issue queue entries Grant 10,922,087 - Karve , et al. February 16, 2	2021-02-16
Buffered instruction dispatching to an issue queue Grant 10,901,744 - Karve , et al. January 26, 2	2021-01-26
Issue queue with dynamic shifting between ports Grant 10,884,753 - Sinharoy , et al. January 5, 2	2021-01-05
Ultra-low Precision Floating-point Fused Multiply-accumulate Unit App 20200387351 - AGRAWAL; Ankur ; et al.	2020-12-10
Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor Grant 10,802,829 - Silberman , et al. October 13, 2	2020-10-13
Executing load-store operations without address translation hardware per load-store unit port Grant 10,776,113 - Gonzalez , et al. Sept	2020-09-15
Wide vector execution in single thread mode for an out-of-order processor Grant 10,713,056 - Mueller , et al.	2020-07-14
Wide vector execution in single thread mode for an out-of-order processor Grant 10,705,847 - Mueller , et al.	2020-07-07
Handling Effective Address Synonyms In A Load-store Unit That Operates Without Address Translation App 20200183689 - LLOYD; BRYAN ; et al.	2020-06-11
Coalescing Global Completion Table Entries In An Out-of-order Processor App 20200150969 - Silberman; Joel A. ; et al.	2020-05-14
Executing load-store operations without address translation hardware per load-store unit port Grant 10,628,158 - Gonzalez , et al.	2020-04-21
Allocating and deallocating reorder queue entries for an out-of-order processor Grant 10,628,166 - Lloyd , et al.	2020-04-21
Handling effective address synonyms in a load-store unit that operates without address translation Grant 10,606,592 - Lloyd , et al.	2020-03-31
Effective address based load store unit in out of order processors Grant 10,606,590 - Lloyd , et al.	2020-03-31
Effective address based load store unit in out of order processors Grant 10,606,593 - Lloyd , et al.	2020-03-31
Handling effective address synonyms in a load-store unit that operates without address translation Grant 10,606,591 - Lloyd , et al.	2020-03-31
Effective address based instruction fetch unit for out of order processors Grant 10,579,384 - Philhower , et al.	2020-03-03
Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor Grant 10,579,387 - Gonzalez , et al.	2020-03-03
Completing coalesced global completion table entries in an out-of-order processor Grant 10,572,264 - Silberman , et al. Feb	2020-02-25
Handling effective address synonyms in a load-store unit that operates without address translation Grant 10,572,256 - Lloyd , et al. Feb	2020-02-25
Handling effective address synonyms in a load-store unit that operates without address translation Grant 10,572,257 - Lloyd , et al. Feb	2020-02-25
Scalable dependency matrix with multiple summary bits in an out-of-order processor Grant 10,564,976 - Silberman , et al. Feb	2020-02-18
Coalescing global completion table entries in an out-of-order processor Grant 10,564,979 - Silberman , et al. Feb	2020-02-18
Load-hit-load detection in an out-of-order processor Grant 10,534,616 - Gonzalez , et al. Ja	2020-01-14
Split store data queue design for an out-of-order processor Grant 10,481,915 - Lloyd , et al. Nov	2019-11-19
Executing Load-store Operations Without Address Translation Hardware Per Load-store Unit Port App 20190310849 - Gonzalez; Christopher ; et al.	2019-10-10
Hazard Detection Of Out-of-order Execution Of Load And Store Instructions In Processors Without Using Real Addresses App 20190310858 - LLOYD; BRYAN ; et al.	2019-10-10
Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses Grant 10,417,002 - Lloyd , et al. Sept	2019-09-17
Executing load-store operations without address translation hardware per load-store unit port Grant 10,394,558 - Gonzalez , et al. A	2019-08-27
Effective address table with multiple taken branch handling for out-of-order processors Grant 10,387,162 - Eickemeyer , et al. A	2019-08-20
Address translation for sending real address to memory subsystem in effective address based load-store unit Grant 10,324,856 - Lloyd , et al.	2019-06-18
Instruction Fusion After Register Rename App 20190179640 - Silberman; Joel A. ; et al.	2019-06-13
Dynamic Fusion Based On Operand Size App 20190179639 - Boersma; Maarten J. ; et al.	2019-06-13
Effective Address Based Instruction Fetch Unit For Out Of Order Processors App 20190179641 - Philhower; Robert A. ; et al.	2019-06-13
Address translation for sending real address to memory subsystem in effective address based load-store unit Grant 10,310,988 - Lloyd , et al.	2019-06-04
Buffered Instruction Dispatching To An Issue Queue App 20190163485 - Karve; Mohit S. ; et al.	2019-05-30
Scalable Dependency Matrix With Multiple Summary Bits In An Out-of-order Processor App 20190163484 - Silberman; Joel A. ; et al.	2019-05-30
Scalable Dependency Matrix With Wake-up Columns For Long Latency Instructions In An Out-of-order Processor App 20190163483 - Silberman; Joel A. ; et al.	2019-05-30
Issue Queue With Dynamic Shifting Between Ports App 20190163486 - Sinharoy; Balaram ; et al.	2019-05-30
Block Based Allocation And Deallocation Of Issue Queue Entries App 20190163489 - Karve; Mohit S. ; et al.	2019-05-30
Completing Coalesced Global Completion Table Entries In An Out-of-order Processor App 20190163491 - Silberman; Joel A. ; et al.	2019-05-30
Coalescing Global Completion Table Entries In An Out-of-order Processor App 20190163490 - Silberman; Joel A. ; et al.	2019-05-30
Scalable Dependency Matrix With A Single Summary Bit In An Out-of-order Processor App 20190163482 - Silberman; Joel A. ; et al.	2019-05-30
Head And Tail Pointer Manipulation In A First-in-first-out Issue Queue App 20190163488 - Karve; Mohit S. ; et al.	2019-05-30
Handling Effective Address Synonyms In A Load-store Unit That Operates Without Address Translation App 20190108025 - Lloyd; Bryan ; et al.	2019-04-11
Handling Effective Address Synonyms In A Load-store Unit That Operates Without Address Translation App 20190108026 - Lloyd; Bryan ; et al.	2019-04-11
Effective Address Based Load Store Unit In Out Of Order Processors App 20190108027 - Lloyd; Bryan ; et al.	2019-04-11
Executing Load-store Operations Without Address Translation Hardware Per Load-store Unit Port App 20190108024 - Gonzalez; Christopher ; et al.	2019-04-11
Handling Effective Address Synonyms In A Load-store Unit That Operates Without Address Translation App 20190108023 - Lloyd; Bryan ; et al.	2019-04-11
Handling Effective Address Synonyms In A Load-store Unit That Operates Without Address Translation App 20190108022 - Lloyd; Bryan ; et al.	2019-04-11
Executing Load-store Operations Without Address Translation Hardware Per Load-store Unit Port App 20190108028 - Gonzalez; Christopher ; et al.	2019-04-11
Address Translation For Sending Real Address To Memory Subsystem In Effective Address Based Load-store Unit App 20190108133 - Lloyd; Bryan ; et al.	2019-04-11
Effective Address Based Load Store Unit In Out Of Order Processors App 20190108021 - Lloyd; Bryan ; et al.	2019-04-11
Load-hit-load Detection In An Out-of-order Processor App 20190108035 - Gonzalez; Christopher ; et al.	2019-04-11
Address Translation For Sending Real Address To Memory Subsystem In Effective Address Based Load-store Unit App 20190108132 - Lloyd; Bryan ; et al.	2019-04-11
Efficient Store-forwarding With Partitioned Fifo Store-reorder Queue In Out-of-order Processor App 20190108031 - Gonzalez; Christopher ; et al.	2019-04-11
Hazard Detection Of Out-of-order Execution Of Load And Store Instructions In Processors Without Using Real Addresses App 20190108034 - Lloyd; Bryan ; et al.	2019-04-11
Load-store Unit With Partitioned Reorder Queues With Single Cam Port App 20190108033 - Gonzalez; Christopher J. ; et al.	2019-04-11
Load-store Unit With Partitioned Reorder Queues With Single Cam Port App 20190108032 - Gonzalez; Christopher J. ; et al.	2019-04-11
Allocating And Deallocating Reorder Queue Entries For An Out-of-order Processor App 20190087195 - Lloyd; Bryan ; et al.	2019-03-21
Split Store Data Queue Design For An Out-of-order Processor App 20190087194 - Lloyd; Bryan J. ; et al.	2019-03-21
Effective Address Table With Multiple Taken Branch Handling For Out-of-order Processors App 20190087196 - Eickemeyer; Richard J. ; et al.	2019-03-21
Wide Vector Execution In Single Thread Mode For An Out-of-order Processor App 20190042265 - Mueller; Silvia M. ; et al.	2019-02-07
Wide Vector Execution In Single Thread Mode For An Out-of-order Processor App 20190042266 - Mueller; Silvia M. ; et al.	2019-02-07
Method and apparatus for dynamically replacing legacy instructions with a single executable instruction utilizing a wide datapath Grant 10,095,524 - Gschwind , et al. October 9, 2	2018-10-09
Probabilistic associative cache Grant 10,019,370 - Abali , et al. July 10, 2	2018-07-10
Data compression accelerator methods, apparatus and design structure with improved resource utilization Grant 9,971,704 - Abali , et al. May 15, 2	2018-05-15
Page table including data fetch width indicator Grant 9,910,781 - Gschwind , et al. March 6, 2	2018-03-06
Page Table Including Data Fetch Width Indicator App 20170097892 - Gschwind; Michael K. ; et al.	2017-04-06
Page table including data fetch width indicator Grant 9,524,100 - Gschwind , et al. December 20, 2	2016-12-20
Page table including data fetch width indicator Grant 9,513,805 - Gschwind , et al. December 6, 2	2016-12-06
Processor and method for partially flushing a dispatched instruction group including a mispredicted branch Grant 9,489,207 - Burky , et al. November 8, 2	2016-11-08
Memory-area property storage including data fetch width indicator Grant 9,483,180 - Gschwind , et al. November 1, 2	2016-11-01
Memory-area property storage including data fetch width indicator Grant 9,483,179 - Gschwind , et al. November 1, 2	2016-11-01
Probabilistic Associative Cache App 20160314072 - Abali; Bulent ; et al.	2016-10-27
Data Compression Accelerator Methods, Apparatus and Design Structure with Improved Resource Utilization App 20160283398 - Abali; Bulent ; et al.	2016-09-29
Probabilistic associative cache Grant 9,424,194 - Abali , et al. August 23, 2	2016-08-23
Techniques for cache injection in a processor system using a cache injection instruction Grant 9,256,540 - Arimilli , et al. February 9, 2	2016-02-09
Memory-area Property Storage Including Data Fetch Width Indicator App 20150293851 - Gschwind; Michael K. ; et al.	2015-10-15
Page Table Including Data Fetch Width Indicator App 20150293703 - Gschwind; Michael K. ; et al.	2015-10-15
Page Table Including Data Fetch Width Indicator App 20150293855 - Gschwind; Michael K. ; et al.	2015-10-15
Memory-area Property Storage Including Data Fetch Width Indicator App 20150293704 - Gschwind; Michael K. ; et al.	2015-10-15
Techniques for cache injection in a processor system Grant 9,110,885 - Arimilli , et al. August 18, 2	2015-08-18
Hardware assist thread for increasing code parallelism Grant 9,037,837 - Hall , et al. May 19, 2	2015-05-19
Processor with resource usage counters for per-thread accounting Grant 9,003,417 - Armstrong , et al. April 7, 2	2015-04-07
Method And Apparatus For The Dynamic Creation Of Instructions Utilizing A Wide Datapath App 20150082009 - Gschwind; Michael ; et al.	2015-03-19
Assist thread for injecting cache memory in a microprocessor Grant 8,949,837 - Bohrer , et al. February 3, 2	2015-02-03
Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath Grant 8,904,151 - Gschwind , et al. December 2, 2	2014-12-02
Prefetch engine based translation prefetching Grant 8,806,177 - Krieger , et al. August 12, 2	2014-08-12
Use of a helper thread to asynchronously compute incoming data Grant 8,775,778 - Arimilli , et al. July 8, 2	2014-07-08
Thread partitioning in a multi-core environment Grant 8,707,016 - Arimilli , et al. April 22, 2	2014-04-22
Hardware assist thread for dynamic performance profiling Grant 8,612,730 - Hall , et al. December 17, 2	2013-12-17
General purpose register cloning Grant 8,601,241 - Arimilli , et al. December 3, 2	2013-12-03
Varying a data prefetch size based upon data usage Grant 8,595,443 - Arimilli , et al. November 26, 2	2013-11-26
Probabilistic Associative Cache App 20130297879 - Abali; Bulent ; et al.	2013-11-07
Scheduling threads having complementary functional unit usage on SMT processors Grant 8,495,649 - Krieger , et al. July 23, 2	2013-07-23
Block driven computation using a caching policy specified in an operand data structure Grant 8,458,439 - Arimilli , et al. June 4, 2	2013-06-04
Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes Grant 8,458,709 - Armstrong , et al. June 4, 2	2013-06-04
Techniques for cache injection in a processor system responsive to a specific instruction sequence Grant 8,443,146 - Arimilli , et al. May 14, 2	2013-05-14
Techniques for cache injection in a processor system with replacement policy position modification Grant 8,429,349 - Arimilli , et al. April 23, 2	2013-04-23
Hardware assist thread for increasing code parallelism Grant 8,423,750 - Hall , et al. April 16, 2	2013-04-16
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors Grant 8,418,180 - Bishop , et al. April 9, 2	2013-04-09
Operand data structure for block computation Grant 8,407,680 - Arimilli , et al. March 26, 2	2013-03-26
Completion arbitration for more than two threads based on resource limitations Grant 8,386,753 - Eisen , et al. February 26, 2	2013-02-26
Speculative popcount data creation Grant 8,387,065 - Arimilli , et al. February 26, 2	2013-02-26
Helper thread for pre-fetching data Grant 8,359,589 - Arimilli , et al. January 22, 2	2013-01-22
Reporting of partially performed memory move Grant 8,356,151 - Arimilli , et al. January 15, 2	2013-01-15
Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor Grant 8,347,068 - Eickemeyer , et al. January 1, 2	2013-01-01
Cache management during asynchronous memory move operations Grant 8,327,101 - Arimilli , et al. December 4, 2	2012-12-04
Computation table for block computation Grant 8,327,345 - Arimilli , et al. December 4, 2	2012-12-04
Block driven computation with an address generation accelerator Grant 8,285,971 - Arimilli , et al. October 9, 2	2012-10-09
Hardware Assist Thread for Increasing Code Parallelism App 20120254594 - Hall; Ronald P. ; et al.	2012-10-04
Specifying an addressing relationship in an operand data structure Grant 8,281,106 - Arimilli , et al. October 2, 2	2012-10-02
Asynchronous memory move across physical nodes with dual-sided communication Grant 8,275,963 - Arimilli , et al. September 25, 2	2012-09-25
Varying an amount of data retrieved from memory based upon an instruction hint Grant 8,266,381 - Arimilli , et al. September 11, 2	2012-09-11
Method and system for managing cache injection in a multiprocessor system Grant 8,255,591 - Bohrer , et al. August 28, 2	2012-08-28
Processor With Resource Usage Counters For Per-thread Accounting App 20120216210 - Armstrong; William Joseph ; et al.	2012-08-23
Sourcing differing amounts of prefetch data in response to data prefetch requests Grant 8,250,307 - Arimilli , et al. August 21, 2	2012-08-21
Mechanisms for communicating with an asynchronous memory mover to perform AMM operations Grant 8,245,004 - Arimilli , et al. August 14, 2	2012-08-14
Assist Thread For Injecting Cache Memory In A Microprocessor App 20120198459 - Bohrer; Patrick Joseph ; et al.	2012-08-02
Assist thread for injecting cache memory in a microprocessor Grant 8,230,422 - Bohrer , et al. July 24, 2	2012-07-24
Techniques for prediction-based indirect data prefetching Grant 8,209,488 - Arimilli , et al. June 26, 2	2012-06-26
Processor core with per-thread resource usage accounting logic Grant 8,209,698 - Armstrong , et al. June 26, 2	2012-06-26
Specifying an access hint for prefetching limited use data in a cache hierarchy Grant 8,176,254 - Frey , et al. May 8, 2	2012-05-08
Data prefetching using indirect addressing Grant 8,166,277 - Arimilli , et al. April 24, 2	2012-04-24
Techniques for data prefetching using indirect addressing with offset Grant 8,161,264 - Arimilli , et al. April 17, 2	2012-04-17
Techniques for indirect data prefetching Grant 8,161,263 - Arimilli , et al. April 17, 2	2012-04-17
Techniques for multi-level indirect data prefetching Grant 8,161,265 - Arimilli , et al. April 17, 2	2012-04-17
Apparatus for randomizing instruction thread interleaving in a multi-thread processor Grant 8,145,885 - Kalla , et al. March 27, 2	2012-03-27
Specifying an access hint for prefetching partial cache block data in a cache hierarchy Grant 8,140,759 - Frey , et al. March 20, 2	2012-03-20
Efficient and flexible memory copy operation Grant 8,140,801 - Arimilli , et al. March 20, 2	2012-03-20
System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory Grant 8,140,764 - Shen , et al. March 20, 2	2012-03-20
Tracking effective addresses in an out-of-order processor Grant 8,131,976 - Doing , et al. March 6, 2	2012-03-06
Group formation with multiple taken branches per group Grant 8,127,115 - Doing , et al. February 28, 2	2012-02-28
Fully asynchronous memory mover Grant 8,095,758 - Arimilli , et al. January 10, 2	2012-01-10
Dependency tracking for enabling successive processor instructions to issue Grant 8,086,826 - Brown , et al. December 27, 2	2011-12-27
Hardware Assist Thread For Dynamic Performance Profiling App 20110302395 - Hall; Ronald P. ; et al.	2011-12-08
Hardware Assist Thread for Increasing Code Parallelism App 20110283095 - Hall; Ronald P. ; et al.	2011-11-17
Information handling system with real and virtual load/store instruction issue queue Grant 8,041,928 - Burky , et al. October 18, 2	2011-10-18
Launching multiple concurrent memory moves via a fully asynchronoous memory mover Grant 8,015,380 - Arimilli , et al. September 6, 2	2011-09-06
Remote asynchronous data mover Grant 7,996,564 - Arimilli , et al. August 9, 2	2011-08-09
Completion of asynchronous memory move in the presence of a barrier operation Grant 7,991,981 - Arimilli , et al. August 2, 2	2011-08-02
Performing an asynchronous memory move (AMM) via execution of AMM store instruction within the instruction set architecture Grant 7,958,327 - Arimilli , et al. June 7, 2	2011-06-07
Scheduling for functional units on simultaneous multi-threaded processors App 20110126200 - Krieger; Orran Y. ; et al.	2011-05-26
Mechanism for avoiding check stops in speculative accesses while operating in real mode Grant 7,949,859 - Kalla , et al. May 24, 2	2011-05-24
Specialized memory move barrier operations Grant 7,941,627 - Arimilli , et al. May 10, 2	2011-05-10
Cache Reconfiguration Based On Run-time Performance Data Or Software Hint App 20110107032 - Shen; Xiaowei ; et al.	2011-05-05
Termination of in-flight asynchronous memory move Grant 7,937,570 - Arimilli , et al. May 3, 2	2011-05-03
Methods and arrangements to manage on-chip memory to reduce memory latency Grant 7,934,061 - da Silva , et al. April 26, 2	2011-04-26
Handling of address conflicts during asynchronous memory move operations Grant 7,930,504 - Arimilli , et al. April 19, 2	2011-04-19
Method for enabling direct prefetching of data during asychronous memory move operation Grant 7,921,275 - Arimilli , et al. April 5, 2	2011-04-05
Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint Grant 7,913,041 - Shen , et al. March 22, 2	2011-03-22
Cache residence prediction Grant 7,904,657 - Shen , et al. March 8, 2	2011-03-08
Cache injection using semi-synchronous memory copy operation Grant 7,890,703 - Arimilli , et al. February 15, 2	2011-02-15
Validity of address ranges used in semi-synchronous memory copy operations Grant 7,882,321 - Arimilli , et al. February 1, 2	2011-02-01
Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor Grant 7,870,406 - Arndt , et al. January 11, 2	2011-01-11
Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements Grant 7,844,778 - Shen , et al. November 30, 2	2010-11-30
Thread Partitioning in a Multi-Core Environment App 20100299496 - Arimilli; Ravi K. ; et al.	2010-11-25
Data Processing System, Processor And Method For Varying A Data Prefetch Size Based Upon Data Usage App 20100293339 - ARIMILLI; RAVI K. ; et al.	2010-11-18
General Purpose Register Cloning App 20100293359 - Arimilli; Ravi K. ; et al.	2010-11-18
Intelligent Cache Replacement Mechanism With Varying And Adaptive Temporal Residency Requirements App 20100281218 - Shen; Xiaowei ; et al.	2010-11-04
Apparatus for adjusting instruction thread priority in a multi-thread processor Grant 7,827,388 - Ward, III , et al. November 2, 2	2010-11-02
Specifying An Access Hint For Prefetching Limited Use Data In A Cache Hierarchy App 20100268885 - Frey; Bradly G. ; et al.	2010-10-21
Specifying An Access Hint For Prefetching Partial Cache Block Data In A Cache Hierarchy App 20100268886 - Frey; Bradly George ; et al.	2010-10-21
Speculative Popcount Data Creation App 20100269118 - Arimilli; Ravi K. ; et al.	2010-10-21
Remote Asynchronous Data Mover App 20100268788 - Arimilli; Lakshminarayana B. ; et al.	2010-10-21
Tracking Effective Addresses in an Out-of-Order Processor App 20100262806 - Doing; Richard W. ; et al.	2010-10-14
Partial Flush Handling with Multiple Branches Per Group App 20100262807 - Burky; William E. ; et al.	2010-10-14
Detecting and Handling Short Forward Branch Conversion Candidates App 20100262813 - Brown; Mary D. ; et al.	2010-10-14
Completion Arbitration for More than Two Threads Based on Resource Limitations App 20100262967 - Eisen; Susan E. ; et al.	2010-10-14
System and Method for Group Formation with Multiple Taken Branches Per Group App 20100257340 - Doing; Richard William ; et al.	2010-10-07
Universal register rename mechanism for instructions with multiple targets in a microprocessor Grant 7,809,929 - Le , et al. October 5, 2	2010-10-05
Dependency Tracking For Enabling Successive Processor Instructions To Issue App 20100250900 - Brown; Mary Douglass ; et al.	2010-09-30
Prefetch engine based translation prefetching App 20100250853 - Krieger; Orran Y. ; et al.	2010-09-30
Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches Grant 7,779,232 - Doing , et al. August 17, 2	2010-08-17
Method and apparatus for preventing soft error accumulation in register arrays Grant 7,774,654 - Bose , et al. August 10, 2	2010-08-10
Universal register rename mechanism for targets of different instruction types in a microprocessor Grant 7,765,384 - Le , et al. July 27, 2	2010-07-27
Information Handling System With Real And Virtual Load/store Instruction Issue Queue App 20100161945 - Burky; William E. ; et al.	2010-06-24
Block Driven Computation Using A Caching Policy Specified In An Operand Data Structure App 20100153648 - Arimilli; Ravi K. ; et al.	2010-06-17
Specifying an Addressing Relationship In An Operand Data Structure App 20100153683 - Arimilli; Ravi K. ; et al.	2010-06-17
Block Driven Computation With An Address Generation Accelerator App 20100153681 - Arimilli; Ravi K. ; et al.	2010-06-17
Operand Data Structure For Block Computation App 20100153931 - Arimilli; Ravi K. ; et al.	2010-06-17
Computation Table For Block Computation App 20100153938 - Arimilli; Ravi K. ; et al.	2010-06-17
Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit Grant 7,725,682 - Gschwind , et al. May 25, 2	2010-05-25
Data processing system, processor and method of data processing having improved branch target address cache Grant 7,707,396 - Bradford , et al. April 27, 2	2010-04-27
Techniques for Cache Injection in a Processor System with Replacement Policy Position Modification App 20100070712 - Arimilli; Lakshminarayana B. ; et al.	2010-03-18
Techniques for Cache Injection in a Processor System Responsive to a Specific Instruction Sequence App 20100070717 - Arimilli; Lakshminarayana B. ; et al.	2010-03-18
Techniques for Cache Injection in a Processor System App 20100070710 - Arimilli; Lakshminarayana B. ; et al.	2010-03-18
Techniques for Cache Injection in a Processor System Using a Cache Injection Instruction App 20100070711 - Arimilli; Lakshminarayana B. ; et al.	2010-03-18
Location-aware cache-to-cache transfers Grant 7,676,637 - Shen , et al. March 9, 2	2010-03-09
Processor core with per-thread resource usage accounting logic App 20100037233 - Armstrong; William Joseph ; et al.	2010-02-11
Method and system for dependency tracking and flush recovery for an out-of-order microprocessor Grant 7,660,971 - Agarwal , et al. February 9, 2	2010-02-09
Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor Grant 7,657,893 - Armstrong , et al. February 2, 2	2010-02-02
Mechanism to save and restore cache and translation trace for fast context switch Grant 7,634,642 - Hochschild , et al. December 15, 2	2009-12-15
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors Grant 7,631,308 - Bishop , et al. December 8, 2	2009-12-08
Latency-aware thread scheduling in non-uniform cache architecture systems Grant 7,574,562 - Shen , et al. August 11, 2	2009-08-11
Handling Of Address Conflicts During Asynchronous Memory Move Operations App 20090198938 - ARIMILLI; RAVI K. ; et al.	2009-08-06
Helper Thread for Pre-Fetching Data App 20090199170 - Arimilli; Ravi K. ; et al.	2009-08-06
Use of a Helper Thread to Asynchronously Compute Incoming Data App 20090199181 - Arimilli; Ravi K. ; et al.	2009-08-06
Completion Of Asynchronous Memory Move In The Presence Of A Barrier Operation App 20090198963 - Arimilli; Ravi K. ; et al.	2009-08-06
Specialized Memory Move Barrier Operations App 20090198917 - Arimilli; Ravi K. ; et al.	2009-08-06
Techniques for Data Prefetching Using Indirect Addressing App 20090198948 - Arimilli; Ravi K. ; et al.	2009-08-06
Techniques for Data Prefetching Using Indirect Addressing with Offset App 20090198904 - Arimilli; Ravi K. ; et al.	2009-08-06
Termination Of In-flight Asynchronous Memory Move App 20090198975 - Arimilli; Ravi K. ; et al.	2009-08-06
Techniques for Prediction-Based Indirect Data Prefetching App 20090198905 - Arimilli; Ravi K. ; et al.	2009-08-06
Techniques for Indirect Data Prefetching App 20090198950 - Arimilli; Ravi K. ; et al.	2009-08-06
Fully Asynchronous Memory Mover App 20090198934 - Arimilli; Ravi K. ; et al.	2009-08-06
Reporting Of Partially Performed Memory Move App 20090198936 - Arimilli; Ravi K. ; et al.	2009-08-06
Method For Enabling Direct Prefetching Of Data During Asychronous Memory Move Operation App 20090198908 - ARIMILLI; RAVI K. ; et al.	2009-08-06
Cache Management During Asynchronous Memory Move Operations App 20090198897 - Arimilli; Ravi K. ; et al.	2009-08-06
Launching Multiple Concurrent Memory Moves Via A Fully Asynchronoous Memory Mover App 20090198939 - Arimilli; Ravi K. ; et al.	2009-08-06
Method And System For Sourcing Differing Amounts Of Prefetch Data In Response To Data Prefetch Requests App 20090198965 - ARIMILLI; RAVI K. ; et al.	2009-08-06
Asynchronous Memory Move Across Physical Nodes (dual-sided Communication For Memory Move) App 20090198955 - Arimilli; Ravi K. ; et al.	2009-08-06
Techniques for Multi-Level Indirect Data Prefetching App 20090198906 - Armilli; Ravi K. ; et al.	2009-08-06
Mechanisms For Communicating With An Asynchronous Memory Mover To Perform Amm Operations App 20090198937 - Arimilli; Ravi K. ; et al.	2009-08-06
Data Processing System, Processor And Method That Support A Touch Of A Partial Cache Line Of Data App 20090198910 - ARIMILLI; RAVI K. ; et al.	2009-08-06
Data Processing System, Processor And Method That Vary An Amount Of Data Retrieved From Memory Based Upon A Hint App 20090198903 - ARIMILLI; RAVI K. ; et al.	2009-08-06
Method And System For Performing An Asynchronous Memory Move (amm) Via Execution Of Amm Store Instruction Within Instruction Set Architecture App 20090198935 - ARIMILLI; RAVI K. ; et al.	2009-08-06
Mechanism for Avoiding Check Stops in Speculative Accesses While Operating in Real Mode App 20090193233 - Kalla; Ronald N. ; et al.	2009-07-30
Validity Of Address Ranges Used In Semi-synchronous Memory Copy Operations App 20090182968 - ARIMILLI; RAVI K. ; et al.	2009-07-16
Latency-aware Thread Scheduling In Non-uniform Cache Architecture Systems App 20090178052 - Shen; Xiaowei ; et al.	2009-07-09
Dynamic Switching Of Multithreaded Processor Between Single Threaded And Simultaneous Multithreaded Modes App 20090144737 - Armstrong; William Joseph ; et al.	2009-06-04
Cache Injection Using Semi-synchronous Memory Copy Operation App 20090138664 - Arimilli; Ravi K. ; et al.	2009-05-28
Propagating data using mirrored lock caches Grant 7,523,260 - Arimilli , et al. April 21, 2	2009-04-21
Method and apparatus for register renaming using multiple physical register files and avoiding associative search Grant 7,506,139 - Burky , et al. March 17, 2	2009-03-17
Validity of address ranges used in semi-synchronous memory copy operations Grant 7,506,132 - Arimilli , et al. March 17, 2	2009-03-17
Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches App 20090063819 - Doing; Richard W. ; et al.	2009-03-05
Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search App 20090055631 - Burky; William E. ; et al.	2009-02-26
Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes Grant 7,496,915 - Armstrong , et al. February 24, 2	2009-02-24
Method and apparatus for preventing soft error accumulation in register arrays Grant 7,493,523 - Bose , et al. February 17, 2	2009-02-17
Cache injection semi-synchronous memory copy operation Grant 7,484,062 - Arimilli , et al. January 27, 2	2009-01-27
Cache Residence Prediction App 20090024797 - Shen; Xiaowei ; et al.	2009-01-22
Method for resource balancing using dispatch flush in a simultaneous multithread processor Grant 7,469,407 - Burky , et al. December 23, 2	2008-12-23
Method And Apparatus For Preventing Soft Error Accumulation In Register Arrays App 20080313509 - Bose; Pradip ; et al.	2008-12-18
Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache Grant 7,467,280 - Shen , et al. December 16, 2	2008-12-16
Efficient And Flexible Memory Copy Operation App 20080307182 - Arimilli; Ravi K. ; et al.	2008-12-11
Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors App 20080294884 - Bishop; James Wilson ; et al.	2008-11-27
Efficient and flexible memory copy operation Grant 7,454,585 - Arimilli , et al. November 18, 2	2008-11-18
System And Structure For Synchronized Thread Priority Selection In A Deeply Pipelined Multithreaded Microprocessor App 20080263325 - Kudva; Prabhakar ; et al.	2008-10-23
Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor App 20080263331 - Le; Hung Q. ; et al.	2008-10-23
Methods and Arrangements to Manage On-Chip Memory to Reduce Memory Latency App 20080263284 - da Silva; Dilma Menezes ; et al.	2008-10-23
Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor App 20080263321 - Le; Hung Q. ; et al.	2008-10-23
Cache Reconfiguration Based On Run-time Performance Data Or Software Hint App 20080263278 - Shen; Xiaowei ; et al.	2008-10-23
Methods and arrangements to manage on-chip memory to reduce memory latency Grant 7,437,517 - da Silva , et al. October 14, 2	2008-10-14
Multi-Mode Register Rename Mechanism for a Highly Threaded Simultaneous Multi-Threaded Microprocessor App 20080250226 - Eickemeyer; Richard James ; et al.	2008-10-09
Configurable Microprocessor App 20080229065 - Le; Hung Qui ; et al.	2008-09-18
Configurable Microprocessor App 20080229058 - Le; Hung Qui ; et al.	2008-09-18
Adaptive Fetch Gating In Multithreaded Processors, Fetch Control And Method Of Controlling Fetches App 20080229068 - BOSE; PRADIP ; et al.	2008-09-18
Method and System for Dependency Tracking and Flush Recovery for an Out-Of-Order Microprocessor App 20080189535 - Agarwal; Vikas ; et al.	2008-08-07
Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor Grant 7,401,208 - Kalla , et al. July 15, 2	2008-07-15
Apparatus and method for adjusting instruction thread priority in a multi-thread processor Grant 7,401,207 - Kalla , et al. July 15, 2	2008-07-15
Apparatus For Selecting An Instruction Thread For Processing In A Multi-thread Processor App 20080162904 - Kalla; Ronald Nick ; et al.	2008-07-03
Apparatus For Adjusting Instruction Thread Priority In A Multi-thread Processor App 20080155233 - Ward; John Wesley ; et al.	2008-06-26
Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches Grant 7,392,366 - Bose , et al. June 24, 2	2008-06-24
Adaptive Fetch Gating In Multithreaded Processors, Fetch Control And Method Of Controlling Fetches App 20080133886 - BOSE; PRADIP ; et al.	2008-06-05
Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache App 20080120496 - Bradford; Jeffrey P. ; et al.	2008-05-22
Method For Changing A Thread Priority In A Simultaneous Multithread Processor App 20080109640 - Burky; William E. ; et al.	2008-05-08
Mechanism for avoiding check stops in speculative accesses while operating in real mode Grant 7,370,177 - Kalla , et al. May 6, 2	2008-05-06
Method for changing a thread priority in a simultaneous multithread processor Grant 7,363,625 - Burky , et al. April 22, 2	2008-04-22
Method and apparatus for selecting an instruction thread for processing in a multi-thread processor Grant 7,360,062 - Kalla , et al. April 15, 2	2008-04-15
Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search App 20080016324 - Burky; William E. ; et al.	2008-01-17
Mechanism to save and restore cache and translation trace for fast context switch App 20080010442 - Hochschild; Peter H. ; et al.	2008-01-10
Cache reconfiguration based on run-time performance data or software hint App 20080010408 - Shen; Xiaowei ; et al.	2008-01-10
Method and apparatus for the dynamic creation of instructions utilizing a wide datapath App 20070260855 - Gschwind; Michael ; et al.	2007-11-08
Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing Grant 7,287,122 - Rajamony , et al. October 23, 2	2007-10-23
Method and apparatus for preventing soft error accumulation in register arrays App 20070220366 - Bose; Pradip ; et al.	2007-09-20
Cache residence prediction Grant 7,266,642 - Shen , et al. September 4, 2	2007-09-04
Enhanced STCX design to improve subsequent load efficiency Grant 7,254,678 - Alexander , et al. August 7, 2	2007-08-07
Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit App 20070162726 - Gschwind; Michael ; et al.	2007-07-12
Cache injection semi-synchronous memory copy operation App 20070150659 - Arimilli; Ravi K. ; et al.	2007-06-28
Propagating data using mirrored lock caches App 20070150665 - Arimilli; Ravi K. ; et al.	2007-06-28
Efficient and flexible memory copy operation App 20070150676 - Arimilli; Ravi K. ; et al.	2007-06-28
Validity of address ranges used in semi-synchronous memory copy operations App 20070150675 - Arimilli; Ravi K. ; et al.	2007-06-28
Enabling and disabling cache bypass using predicted cache line usage Grant 7,228,388 - Hu , et al. June 5, 2	2007-06-05
Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions Grant 7,213,135 - Burky , et al. May 1, 2	2007-05-01
Localized cache block flush instruction Grant 7,194,587 - McCalpin , et al. March 20, 2	2007-03-20
Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor Grant 7,155,600 - Burky , et al. December 26, 2	2006-12-26
Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor Grant 7,143,267 - Fluhr , et al. November 28, 2	2006-11-28
Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment Grant 7,120,784 - Alexander , et al. October 10, 2	2006-10-10
Enhanced STCX design to improve subsequent load efficiency App 20060212653 - Alexander; Gregory William ; et al.	2006-09-21
Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors App 20060184946 - Bishop; James Wilson ; et al.	2006-08-17
Recovery of global history vector in the event of a non-branch flush Grant 7,093,111 - Frommer , et al. August 15, 2	2006-08-15
Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor App 20060173665 - Arndt; Richard Louis ; et al.	2006-08-03
Assist thread for injecting cache memory in a microprocessor App 20060155963 - Bohrer; Patrick Joseph ; et al.	2006-07-13
Methods and arrangements to manage on-chip memory to reduce memory latency App 20060155886 - da Silva; Dilma Menezes ; et al.	2006-07-13
Enabling and disabling cache bypass using predicted cache line usage App 20060112233 - Hu; Zhigang ; et al.	2006-05-25
Performance throttling for temperature reduction in a microprocessor Grant 7,051,221 - Clabes , et al. May 23, 2	2006-05-23
Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches App 20060101238 - Bose; Pradip ; et al.	2006-05-11
Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions Grant 7,039,768 - Alexander , et al. May 2, 2	2006-05-02
Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache Grant 7,032,097 - Alexander , et al. April 18, 2	2006-04-18
Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing App 20060080506 - Rajamony; Ramakrishnan ; et al.	2006-04-13
Method and system for managing cache injection in a multiprocessor system App 20060064518 - Bohrer; Patrick Joseph ; et al.	2006-03-23
Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread Grant 7,000,233 - Levitan , et al. February 14, 2	2006-02-14
Branch prediction circuits and methods and systems using the same Grant 7,000,096 - Sinharoy February 14, 2	2006-02-14
Atomic quad word storage in a simultaneous multithreaded system Grant 6,981,128 - Fluhr , et al. December 27, 2	2005-12-27
Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables Grant 6,976,157 - Sinharoy December 13, 2	2005-12-13
Use of software hint for branch prediction in the absence of hint bit in the branch instruction Grant 6,971,000 - Sinharoy , et al. November 29, 2	2005-11-29
Method and apparatus for capturing event traces for debug and analysis Grant 6,961,875 - Floyd , et al. November 1, 2	2005-11-01
Location-aware cache-to-cache transfers App 20050240735 - Shen, Xiaowei ; et al.	2005-10-27
Cache residence prediction App 20050182907 - Shen, Xiaowei ; et al.	2005-08-18
Apparatus and method for recovering a link stack from mis-speculation Grant 6,910,124 - Sinharoy June 21, 2	2005-06-21
Method and apparatus to dynamically recalibrate VLSI chip thermal sensors through software control Grant 6,879,928 - Clabes , et al. April 12, 2	2005-04-12
Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program Grant 6,877,089 - Sinharoy April 5, 2	2005-04-05
Recovery of global history vector in the event of a non-branch flush App 20050027975 - Frommer, Scott B. ; et al.	2005-02-03
Circuits and methods for recovering link stack data upon branch instruction mis-speculation Grant 6,848,044 - Eisen , et al. January 25, 2	2005-01-25
Apparatus and method for performing branch predictions using dual branch history tables and for updating such branch history tables Grant 6,823,446 - Sinharoy November 23, 2	2004-11-23
Software hint to improve the branch target prediction accuracy Grant 6,823,447 - Hay , et al. November 23, 2	2004-11-23
Method for changing a thread priority in a simultaneous multithread processor App 20040215945 - Burky, William E. ; et al.	2004-10-28
Performance throttling for temperature reduction in a microprocessor App 20040215988 - Clabes, Joachim Gerhard ; et al.	2004-10-28
Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes App 20040215939 - Armstrong, William Joseph ; et al.	2004-10-28
Localized cache block flush instruction App 20040215896 - McCalpin, John David ; et al.	2004-10-28
Cache predictor for simultaneous multi-threaded processor system supporting multiple translations App 20040215882 - Alexander, Gregory William ; et al.	2004-10-28
Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register App 20040215892 - Fluhr, Eric J. ; et al.	2004-10-28
Method and logical apparatus for managing thread execution in a simultaneous multi-threaded (SMT) processor App 20040215932 - Burky, William Elton ; et al.	2004-10-28
Method and apparatus for selecting an instruction thread for processing in a multi-thread processor App 20040215946 - Kalla, Ronald Nick ; et al.	2004-10-28
Method using a dispatch flush in a simultaneous multithread processor to resolve exception conditions App 20040215944 - Burky, William E. ; et al.	2004-10-28
Split branch history tables and count cache for simultaneous multithreading App 20040215720 - Alexander, Gregory William ; et al.	2004-10-28
Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor App 20040215947 - Ward, John Wesley III ; et al.	2004-10-28
Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache App 20040215921 - Alexander, Gregory W. ; et al.	2004-10-28
Apparatus and method for adjusting instruction thread priority in a multi-thread processor App 20040216106 - Kalla, Ronald Nick ; et al.	2004-10-28
Atomic quad word storage in a simultaneous multithreaded system App 20040216104 - Fluhr, Eric J. ; et al.	2004-10-28
Method for resource balancing using dispatch flush in a simultaneous multithread processor App 20040216105 - Burky, William E. ; et al.	2004-10-28
Method and logical apparatus for managing resource redistribution in a simultaneous multi-threaded (SMT) processor App 20040216101 - Burky, William Elton ; et al.	2004-10-28
Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor App 20040216113 - Armstrong, William Joseph ; et al.	2004-10-28
Mechanism for avoiding check stops in speculative accesses while operating in real mode App 20040216001 - Kalla, Ronald N. ; et al.	2004-10-28
Method and circuit for modifying pipeline length in a simultaneous multithread processor App 20040210742 - Levitan, David Stephen ; et al.	2004-10-21
Compression of execution path history to improve branch prediction accuracy Grant 6,766,443 - Sinharoy July 20, 2	2004-07-20
Prefetching instructions in mis-predicted path for low confidence branches Grant 6,766,441 - Sinharoy July 20, 2	2004-07-20
Guaranteed method and apparatus for capture of debug data Grant 6,760,867 - Floyd , et al. July 6, 2	2004-07-06
Global history vector recovery circuits and methods and systems using the same Grant 6,745,323 - Sinharoy June 1, 2	2004-06-01
Method and system for dynamically shared completion table supporting multiple threads in a processing system Grant 6,721,874 - Le , et al. April 13, 2	2004-04-13
Method and apparatus for capturing event traces for debug and analysis App 20040015880 - Floyd, Michael Stephen ; et al.	2004-01-22
Method for limiting physical resource usage in a virtual tag allocation environment of a microprocessor App 20030182540 - Burky, William Elton ; et al.	2003-09-25
Compression of execution path history to improve branch prediction accuracy App 20020194465 - Sinharoy, Balaram	2002-12-19
Software hint to improve the branch target prediction accuracy App 20020157000 - Hay, Robert William ; et al.	2002-10-24
Circuits and methods for recovering link stack data upon branch instruction mis-speculation App 20020129226 - Eisen, Lee Evan ; et al.	2002-09-12
Guaranteed method and apparatus for capture of debug data App 20020129300 - Floyd, Michael Stephen ; et al.	2002-09-12
Method and system for prefetching instructions in a superscalar processor App 20020099926 - Sinharoy, Balaram	2002-07-25
Branch Prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program App 20020083312 - Sinharoy, Balaram	2002-06-27