loadpatents
name:-0.016484975814819
name:-0.016057968139648
name:-0.0018079280853271
SINGHAL; Vivek Patent Filings

SINGHAL; Vivek

Patent Applications and Registrations

Patent applications and USPTO patent grants for SINGHAL; Vivek.The latest application filed is for "an x-ray mass flow rate sensor for high pressure processes".

Company Profile
1.15.11
  • SINGHAL; Vivek - Austin TX
  • Singhal; Vivek - Bangalore IN
  • Singhal; Vivek - Karnataka IN
  • Singhal; Vivek - San Francisco CA
  • Singhal; Vivek - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
An X-ray Mass Flow Rate Sensor For High Pressure Processes
App 20210033442 - SINGHAL; Vivek ;   et al.
2021-02-04
Method and apparatus for test time reduction using fractional data packing
Grant 9,970,987 - Potty , et al. May 15, 2
2018-05-15
Area-optimized retention flop implementation
Grant 9,705,481 - Srivastava , et al. July 11, 2
2017-07-11
Area-optimized Retention Flop Implementation
App 20170194949 - Srivastava; Sudesh Chandra ;   et al.
2017-07-06
Frequency scaled segmented scan chain for integrated circuits
Grant 9,535,123 - Mittal , et al. January 3, 2
2017-01-03
Method and Apparatus for Test Time Reduction Using Fractional Data Packing
App 20160356849 - Potty; Sreenath Narayanan ;   et al.
2016-12-08
Method and apparatus for test time reduction using fractional data packing
Grant 9,448,284 - Potty , et al. September 20, 2
2016-09-20
Frequency Scaled Segmented Scan Chain for Integrated Circuits
App 20160266202 - Mittal; Rajesh Kumar ;   et al.
2016-09-15
Phase shifted coarse/fine clock dithering responsive to controller select signals
Grant 9,419,630 - Potty , et al. August 16, 2
2016-08-16
Method And Apparatus To Suppress Digital Noise Spurs Using Multi-stage Clock Dithering
App 20160191066 - Potty; Sreenath Narayanan ;   et al.
2016-06-30
Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a multi-power-domain chip
Grant 9,319,045 - Srivastava , et al. April 19, 2
2016-04-19
Method And Apparatus For Test Time Reduction Using Fractional Data Packing
App 20150323596 - Potty; Sreenath Narayanan ;   et al.
2015-11-12
IC delaying flip-flop output partial clock cycle for equalizing current
Grant 9,053,273 - Poddutur , et al. June 9, 2
2015-06-09
Interference mitigation output frequency determined by division factors selected randomly
Grant 8,981,821 - Potty , et al. March 17, 2
2015-03-17
Circuits And Methods For Signal Interference Mitigation
App 20140197875 - Potty; Sreenath Narayanan ;   et al.
2014-07-17
Systems and method for spur supression in a multiple radio SoC
Grant 8,750,805 - Singhal , et al. June 10, 2
2014-06-10
Interference mitigation in mixed signal integrated circuits (ICs)
Grant 8,698,539 - Nayyar , et al. April 15, 2
2014-04-15
Apparatuses And Methods To Suppress Power Supply Noise Harmonics In Integrated Circuits
App 20140021993 - PODDUTUR; SUMANTH REDDY ;   et al.
2014-01-23
SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC
App 20120154010 - Singhal; Vivek ;   et al.
2012-06-21
Consolidated record generation with stable identifiers for data integration systems
Grant 8,185,534 - Singhal , et al. May 22, 2
2012-05-22
Flip-flop Architecture For Mitigating Hold Closure
App 20120062298 - PODDUTUR; Sumanth Reddy ;   et al.
2012-03-15
Circuit for aligning input signals
Grant 8,058,902 - Khurana , et al. November 15, 2
2011-11-15
Dynamic web page cache
Grant 7,096,418 - Singhal , et al. August 22, 2
2006-08-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed