loadpatents
name:-0.0025670528411865
name:-0.010707139968872
name:-0.00065422058105469
Singh; Vinaya Kumar Patent Filings

Singh; Vinaya Kumar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Singh; Vinaya Kumar.The latest application filed is for "automated debugging method and system for over-constrained circuit verification environment".

Company Profile
0.9.3
  • Singh; Vinaya Kumar - Noida N/A IN
  • Singh; Vinaya Kumar - US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Adaptive deadend avoidance in constrained simulation
Grant 8,671,395 - Yuan , et al. March 11, 2
2014-03-11
Automated debugging method for over-constrained circuit verification environment
Grant 8,104,001 - Lehavot , et al. January 24, 2
2012-01-24
Automated debugging method and system for over-constrained circuit verification environment
Grant 8,099,695 - Lehavot , et al. January 17, 2
2012-01-17
Method for providing information associated with an over-constrained event in verification of a circuit design
Grant 8,099,696 - Lehavot , et al. January 17, 2
2012-01-17
Method for checking a status of a signal port to identify an over-constrained event
Grant 7,984,401 - Lehavot , et al. July 19, 2
2011-07-19
Method and system for implementing context aware synthesis of assertions
Grant 7,810,056 - Garg , et al. October 5, 2
2010-10-05
Method and system for handling assertion libraries in functional verification
Grant 7,712,060 - Garg , et al. May 4, 2
2010-05-04
Automated Debugging Method And System For Over-constrained Circuit Verification Environment
App 20090144680 - LEHAVOT; Amir ;   et al.
2009-06-04
Automated Debugging Method And System For Over-constrained Circuit Verification Environment
App 20090144681 - LEHAVOT; Amir ;   et al.
2009-06-04
Automated Debugging Method And System For Over-constrained Circuit Verification Environment
App 20090144683 - Lehavot; Amir ;   et al.
2009-06-04
Design optimization using approximate reachability analysis
Grant 7,428,712 - Singh , et al. September 23, 2
2008-09-23

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed