Singh; Rupesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Singh; Rupesh.The latest application filed is for "data bridge for interfacing source synchronous datapaths with unknown clock phases".

Company Profile

3.10.13

Singh; Rupesh - Ghaziabad IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
First order memory-less dynamic element matching technique Grant 11,417,371 - Bal , et al. August 16, 2	2022-08-16
Clock and data recovery circuit Grant 11,411,565 - Singh , et al. August 9, 2	2022-08-09
Data Bridge For Interfacing Source Synchronous Datapaths With Unknown Clock Phases App 20220206987 - BAL; Ankur ; et al.	2022-06-30
Method And Architecture For Serial Link Characterization By Arbitrary Size Pattern Generator App 20220188203 - BAL; Ankur ; et al.	2022-06-16
High Speed Data Weighted Averaging (dwa) To Binary Converter Circuit App 20220069837 - BAL; Ankur ; et al.	2022-03-03
Method And Device For Testing Successive Approximation Register Analog-to-digital Converters App 20220006467 - BAL; Ankur ; et al.	2022-01-06
First Order Memory-less Dynamic Element Matching Technique App 20210343319 - BAL; Ankur ; et al.	2021-11-04
First order memory-less dynamic element matching technique Grant 11,094,354 - Bal , et al. August 17, 2	2021-08-17
Digital sinusoid generator Grant 11,092,993 - Bal , et al. August 17, 2	2021-08-17
Clock And Data Recovery Circuit App 20210211133 - SINGH; Rupesh ; et al.	2021-07-08
Sigma-delta analog-to-digital converter circuit with correction for mismatch error introduced by the feedback digital-to-analog converter Grant 11,043,960 - Bal , et al. June 22, 2	2021-06-22
High Throughput Digital Filter Architecture For Processing Unary Coded Data App 20210133124 - BAL; Ankur ; et al.	2021-05-06
First Order Memory-less Dynamic Element Matching Technique App 20210110852 - BAL; Ankur ; et al.	2021-04-15
High Throughput Parallel Architecture For Recursive Sinusoid Synthesizer App 20210081174 - BAL; Ankur ; et al.	2021-03-18
Sigma-delta Analog-to-digital Converter Circuit With Correction For Mismatch Error Introduced By The Feedback Digital-to-analog Converter App 20200389180 - BAL; Ankur ; et al.	2020-12-10
Clock jitter measurement using signal-to-noise ratio degradation in a continuous time delta-sigma modulator Grant 10,862,503 - Bal , et al. December 8, 2	2020-12-08
Clock Jitter Measurement Using Signal-to-noise Ratio Degradation In A Continuous Time Delta-sigma Modulator App 20200186162 - BAL; Ankur ; et al.	2020-06-11
Digital Sinusoid Generator App 20190384347 - BAL; Ankur ; et al.	2019-12-19
Latency buffer circuit with adaptable time shift Grant 10,484,165 - Singh , et al. Nov	2019-11-19
Latency Buffer Circuit With Adaptable Time Shift App 20190190688 - Singh; Rupesh ; et al.	2019-06-20
High speed data weighted averaging architecture Grant 10,218,380 - Bal , et al. Feb	2019-02-26
High speed data weighted averaging architecture Grant 10,211,850 - Bal , et al. Feb	2019-02-19
High speed data weighted averaging architecture Grant 10,050,640 - Bal , et al. August 14, 2	2018-08-14

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