Singh; Raminderpal

Patent Applications and Registrations

Patent applications and USPTO patent grants for Singh; Raminderpal.The latest application filed is for "method and system for evaluating a machine tool operating characteristics".

Company Profile

0.16.15

Singh; Raminderpal - Essex Junction VT
Singh; Raminderpal - Cortlandt Manor NY
Singh; Raminderpal - Hopewell Junction NY
Singh; Raminderpal - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for evaluating a machine tool operating characteristics Grant 8,594,826 - Aharoni , et al. November 26, 2	2013-11-26
Method And System For Evaluating A Machine Tool Operating Characteristics App 20130006406 - Aharoni; Ehud ; et al.	2013-01-03
Method and system for evaluating a machine tool operating characteristics Grant 8,285,414 - Aharoni , et al. October 9, 2	2012-10-09
Bias-controlled Deep Trench Substrate Noise Isolation Integrated Circuit Device Structures App 20110291238 - Chapman; Phillip Francis ; et al.	2011-12-01
Bias-controlled deep trench substrate noise isolation integrated circuit device structures Grant 8,021,941 - Chapman , et al. September 20, 2	2011-09-20
Bias-controlled Deep Trench Substrate Noise Isolation Integrated Circuit Device Structures App 20110018094 - Chapman; Phillip Francis ; et al.	2011-01-27
Method And System For Evaluating A Machine Tool Operating Characteristics App 20100249976 - Aharoni; Ehud ; et al.	2010-09-30
Method, Computer Program and System Providing for Semiconductor Processes Optimization App 20090031260 - Angyal; Matthew ; et al.	2009-01-29
Method and apparatus for providing noise suppression in an integrated circuit Grant 7,309,898 - Singh , et al. December 18, 2	2007-12-18
Open system for simulation engines to communicate across multiple sites using a portal methodology Grant 7,246,055 - Singh July 17, 2	2007-07-17
Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction Grant 7,139,990 - Singh , et al. November 21, 2	2006-11-21
Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits Grant 7,089,512 - Iadanza , et al. August 8, 2	2006-08-08
Method and apparatus for providing noise suppression in a integrated circuit Grant 7,020,857 - Singh , et al. March 28, 2	2006-03-28
Method for designing an integrated circuit having multiple voltage domains Grant 7,000,214 - Iadanza , et al. February 14, 2	2006-02-14
Method, program product, and design tool for automatic transmission line selection in application specific integrated circuits Grant 6,954,920 - Jenkins , et al. October 11, 2	2005-10-11
Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction App 20050216873 - Singh, Raminderpal ; et al.	2005-09-29
Method and system for low noise integrated circuit design Grant 6,950,997 - Dickey , et al. September 27, 2	2005-09-27
Method For Optimal Use Of Direct Fit And Interpolated Models In Schematic Custom Design Of Electrical Circuits App 20050204318 - Iadanza, Joseph A. ; et al.	2005-09-15
Method For Designing An Integrated Circuit Having Multiple Voltage Domains App 20050108667 - Iadanza, Joseph A. ; et al.	2005-05-19
Vertically-stacked co-planar transmission line structure for IC design App 20050062137 - Singh, Raminderpal ; et al.	2005-03-24
Method and system for integrated circuit design Grant 6,865,725 - Dickey , et al. March 8, 2	2005-03-08
Method, Program Product, And Design Tool For Automatic Transmission Line Selection In Application Specific Integrated Circuits App 20040268285 - Jenkins, Peter J ; et al.	2004-12-30
Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit Grant 6,826,025 - Singh , et al. November 30, 2	2004-11-30
On chip resistor calibration structure and method Grant 6,825,490 - Hook , et al. November 30, 2	2004-11-30
Method And System For Integrated Circuit Design App 20040216063 - Dickey, Carl E. ; et al.	2004-10-28
Method And System For Low Noise Integrated Circuit Design App 20040216060 - Dickey, Carl E ; et al.	2004-10-28
Multiple chip guard rings for integrated circuit and chip guard ring interconnect Grant 6,744,112 - Johnson , et al. June 1, 2	2004-06-01
Multiple Chip Guard Rings For Integrated Circuit And Chip Guard Ring Interconnect App 20040061183 - Johnson, Jeffrey B. ; et al.	2004-04-01
Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit App 20030214767 - Singh, Raminderpal ; et al.	2003-11-20
Method and apparatus for providing noise suppression in an integrated circuit App 20030214348 - Singh, Raminderpal ; et al.	2003-11-20

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