name:-0.016870021820068
name:-0.017130136489868
name:-0.0013020038604736
Singh; Nirmal Patent Filings

Singh; Nirmal

Patent Applications and Registrations

Patent applications and USPTO patent grants for Singh; Nirmal.The latest application filed is for "utilizing machine learning to detect malicious office documents".

Company Profile
0.10.11
  • Singh; Nirmal - Mohali IN
  • Singh; Nirmal - Chandigarh IN
  • Singh; Nirmal - Sunnyvale CA US
  • Singh; Nirmal - Milford MA
  • Singh; Nirmal - Allen TX
  • Singh; Nirmal - Lenox MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks
Patent Activity
PatentDate
Utilizing Machine Learning to detect malicious Office documents
App 20220083661 - Ma; Changsha ;   et al.
2022-03-17
Utilizing Machine Learning to detect malicious executable files efficiently and effectively
App 20220083659 - Ma; Changsha ;   et al.
2022-03-17
Machine learning to determine domain reputation, content classification, phishing sites, and command and control sites
App 20210377303 - Bui; Loc ;   et al.
2021-12-02
Machine learning to determine command and control sites
App 20210377304 - Ma; Changsha ;   et al.
2021-12-02
Female crotch enhancing article
Grant 9,854,850 - Rana , et al. January 2, 2
2018-01-02
Absorbent article
Grant 9,044,355 - Rana , et al. June 2, 2
2015-06-02
Oxidation catalyst and method for destruction of CO, VOC and halogenated VOC
Grant 8,475,755 - Dang , et al. July 2, 2
2013-07-02
Oxidation Catalyst and Method for Destruction of CO, VOC and Halogenated VOC
App 20110044874 - Dang; Zhongyuan ;   et al.
2011-02-24
Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)
Grant 7,429,880 - Rana , et al. September 30, 2
2008-09-30
Technology dependent transformations for CMOS in digital design synthesis
Grant 7,360,198 - Rana , et al. April 15, 2
2008-04-15
Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)
App 20070262792 - Rana; Amar Pal Singh ;   et al.
2007-11-15
Automatically provisioning a network element
App 20070014230 - Colven; David M. ;   et al.
2007-01-18
Technology dependent transformations for Silicon-On-Insulator in digital design synthesis
Grant 7,039,882 - Rana , et al. May 2, 2
2006-05-02
Technology dependent transformations for CMOS in digital design synthesis
App 20060075375 - Rana; Amar Pal Singh ;   et al.
2006-04-06
Female crotch enhancing article
App 20040154079 - Rana, Amar Pal Singh ;   et al.
2004-08-12
Absorbent article
App 20040068245 - Rana, Amar Pal Singh ;   et al.
2004-04-08
Technology dependent transformations in CMOS and silicon-on-insulator during digital design synthesis
App 20030233628 - Rana, Amar Pal Singh ;   et al.
2003-12-18
Graded insulation cable construction, and method of overcoming stresses therein
Grant 4,132,858 - Anderson , et al. January 2, 1
1979-01-02
Company Registrations
SEC0001610923SINGH NIRMAL

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed