Singh; Harsanjeet

Patent Applications and Registrations

Patent applications and USPTO patent grants for Singh; Harsanjeet.The latest application filed is for "implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing".

Company Profile

0.4.7

Singh; Harsanjeet - Danville CA
Singh; Harsanjeet - Santa Clara CA
Singh; Harsanjeet - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing Grant 9,785,542 - Elston , et al. October 10, 2	2017-10-10
Using shared pins in a concurrent test execution environment Grant 9,274,911 - Elston , et al. March 1, 2	2016-03-01
Implementing Edit And Update Functionality Within A Development Environment Used To Compile Test Plans For Automated Semiconductor Device Testing App 20140310693 - ELSTON; Mark ; et al.	2014-10-16
Method and structure to develop a test program for semiconductor integrated circuits Grant 8,255,198 - Krishnaswamy , et al. August 28, 2	2012-08-28
Method and Structure to Develop a Test Program for Semiconductor Integrated Circuits App 20100192135 - KRISHNASWAMY; Ramachandran ; et al.	2010-07-29
Test Emulator, Test Module Emulator And Record Medium Storing Program Therein App 20080016396 - Higashi; Shinsaku ; et al.	2008-01-17
Test Emulator, Test Module Emulator And Record Medium Storing Program Therein App 20080010524 - Higashi; Shinsaku ; et al.	2008-01-10
Method and structure to develop a test program for semiconductor integrated circuits Grant 7,209,851 - Singh , et al. April 24, 2	2007-04-24
Method and structure to develop a test program for semiconductor integrated circuits App 20050154550 - Singh, Harsanjeet ; et al.	2005-07-14
Test emulator, test module emulator, and record medium storing program therein App 20050039079 - Higashi, Shinsaku ; et al.	2005-02-17
Method and structure to develop a test program for semiconductor integrated circuits App 20040225459 - Krishnaswamy, Ramachandran ; et al.	2004-11-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.