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Sinangil; Mahmut Patent Filings

Sinangil; Mahmut

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sinangil; Mahmut.The latest application filed is for "vertical interconnect structures with integrated circuits".

Company Profile
20.19.24
  • Sinangil; Mahmut - Campbell CA
  • Sinangil; Mahmut - Hsinchu TW
  • Sinangil; Mahmut - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Vertical Interconnect Structures With Integrated Circuits
App 20220302088 - Yang; Tzu-Hsien ;   et al.
2022-09-22
Compute In Memory System
App 20220262424 - Sinangil; Mahmut
2022-08-18
Low voltage memory device
Grant 11,404,114 - Sinangil , et al. August 2, 2
2022-08-02
Compute in memory system
Grant 11,322,195 - Sinangil May 3, 2
2022-05-03
Series Of Parallel Sensing Operations For Multi-level Cells
App 20220130435 - Dong; Qing ;   et al.
2022-04-28
Series of parallel sensing operations for multi-level cells
Grant 11,238,906 - Dong , et al. February 1, 2
2022-02-01
Series Of Parallel Sensing Operations For Multi-level Cells
App 20210390987 - Dong; Qing ;   et al.
2021-12-16
Low voltage bit-cell
Grant 11,200,946 - Sinangil , et al. December 14, 2
2021-12-14
Compute In Memory System
App 20210158854 - Sinangil; Mahmut
2021-05-27
SRAM cell for interleaved wordline scheme
Grant 10,971,217 - Fujiwara , et al. April 6, 2
2021-04-06
Bit Line Logic Circuits And Methods
App 20210090621 - WU; Shang-Chi ;   et al.
2021-03-25
Low Voltage Bit-Cell
App 20210050053 - Sinangil; Mahmut ;   et al.
2021-02-18
Low Voltage Memory Device
App 20210043252 - Sinangil; Mahmut ;   et al.
2021-02-11
Pre-Charging Bit Lines Through Charge-Sharing
App 20200402572 - Sinangil; Mahmut ;   et al.
2020-12-24
Bit line logic circuits and methods
Grant 10,867,646 - Wu , et al. December 15, 2
2020-12-15
Memory read stability enhancement with short segmented bit line architecture
Grant 10,854,282 - Sinangil , et al. December 1, 2
2020-12-01
Sram Cell For Interleaved Wordline Scheme
App 20200372951 - Fujiwara; Hidehiro ;   et al.
2020-11-26
Low voltage bit-cell
Grant 10,847,214 - Sinangil , et al. November 24, 2
2020-11-24
Pre-charging bit lines through charge-sharing
Grant 10,847,217 - Sinangil , et al. November 24, 2
2020-11-24
Low voltage memory device
Grant 10,803,928 - Sinangil , et al. October 13, 2
2020-10-13
SRAM cell for interleaved wordline scheme
Grant 10,770,131 - Fujiwara , et al. Sep
2020-09-08
Memory Read Stability Enhancement With Short Segmented Bit Line Architecture
App 20200075092 - Sinangil; Mahmut ;   et al.
2020-03-05
Low Voltage Memory Device
App 20190385672 - Sinangil; Mahmut ;   et al.
2019-12-19
Memory read stability enhancement with short segmented bit line architecture
Grant 10,510,403 - Sinangil , et al. Dec
2019-12-17
Pre-Charging Bit Lines Through Charge-Sharing
App 20190348110 - Sinangil; Mahmut ;   et al.
2019-11-14
Memory Circuit Bit Line Logic Circuit And Method
App 20190304520 - WU; Shang-Chi ;   et al.
2019-10-03
Pre-charging bit lines through charge-sharing
Grant 10,410,715 - Sinangil , et al. Sept
2019-09-10
Sram Cell For Interleaved Wordline Scheme
App 20190237134 - Fujiwara; Hidehiro ;   et al.
2019-08-01
SRAM cell for interleaved wordline scheme
Grant 10,276,231 - Fujiwara , et al.
2019-04-30
Memory Read Stability Enhancement With Short Segmented Bit Line Architecture
App 20190108874 - Sinangil; Mahmut ;   et al.
2019-04-11
Low Voltage Bit-Cell
App 20190096476 - Chen; Yen-Huei ;   et al.
2019-03-28
Memory read stability enhancement with short segmented bit line architecture
Grant 10,153,038 - Sinangil , et al. Dec
2018-12-11
Memory Read Stability Enhancement With Short Segmented Bit Line Architecture
App 20180197601 - Sinangil; Mahmut ;   et al.
2018-07-12
Pre-Charging Bit Lines Through Charge-Sharing
App 20180174649 - Sinangil; Mahmut ;   et al.
2018-06-21
Sram Cell For Interleaved Wordline Scheme
App 20180158510 - Fujiwara; Hidehiro ;   et al.
2018-06-07
Pre-charging bit lines through charge-sharing
Grant 9,922,701 - Sinangil , et al. March 20, 2
2018-03-20
Memory read stability enhancement with short segmented bit line architecture
Grant 9,922,700 - Sinangil , et al. March 20, 2
2018-03-20
Pre-charging Bit Lines Through Charge-sharing
App 20180040366 - Sinangil; Mahmut ;   et al.
2018-02-08
SRAM cell for interleaved wordline scheme
Grant 9,886,996 - Fujiwara , et al. February 6, 2
2018-02-06
Memory Read Stability Enhancement With Short Segmented Bit Line Architecture
App 20170345485 - Sinangil; Mahmut ;   et al.
2017-11-30
Level Shifter Circuit Using Boosting Circuit
App 20170264276 - Sinangil; Mahmut ;   et al.
2017-09-14
Level shifter circuit using boosting circuit
Grant 9,762,216 - Sinangil , et al. September 12, 2
2017-09-12
Sram Cell For Interleaved Wordline Scheme
App 20170110181 - Fujiwara; Hidehiro ;   et al.
2017-04-20

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