loadpatents
name:-0.01570987701416
name:-0.010651111602783
name:-0.00053596496582031
Simmons-Matthews; Margaret Patent Filings

Simmons-Matthews; Margaret

Patent Applications and Registrations

Patent applications and USPTO patent grants for Simmons-Matthews; Margaret.The latest application filed is for "die having through-substrate vias with deformation protected tips".

Company Profile
0.10.12
  • Simmons-Matthews; Margaret - Richardson TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
Grant 8,815,642 - West , et al. August 26, 2
2014-08-26
TCE compensation for package substrates for reduced die warpage assembly
Grant 8,759,154 - Simmons-Matthews June 24, 2
2014-06-24
Die Having Through-substrate Vias With Deformation Protected Tips
App 20140151895 - WEST; JEFFREY ALAN ;   et al.
2014-06-05
Through-silicon Via (tsv) Die And Method To Control Warpage
App 20140124900 - WEST; JEFFREY ALAN ;   et al.
2014-05-08
Laser-Assisted Cleaving of a Reconstituted Wafer for Stacked Die Assemblies
App 20140038359 - West; Jeffrey Alan ;   et al.
2014-02-06
Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
Grant 8,575,758 - West , et al. November 5, 2
2013-11-05
Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate
Grant 8,471,577 - Stillman , et al. June 25, 2
2013-06-25
Laser-assisted Cleaving Of A Reconstituted Wafer For Stacked Die Assemblies
App 20130032946 - WEST; JEFFREY ALAN ;   et al.
2013-02-07
TCE Compensation for Package Substrates for Reduced Die Warpage Assembly
App 20130029457 - Simmons-Matthews; Margaret
2013-01-31
Through carrier dual side loop-back testing of TSV die after die attach to substrate
Grant 8,344,749 - Stillman , et al. January 1, 2
2013-01-01
Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips
Grant 8,344,493 - West , et al. January 1, 2
2013-01-01
TCE compensation for package substrates for reduced die warpage assembly
Grant 8,298,863 - Simmons-Matthews October 30, 2
2012-10-30
Warpage Control Features On The Bottomside Of Tsv Die Lateral To Protruding Bottomside Tips
App 20120175774 - West; Jeffrey Alan ;   et al.
2012-07-12
Lateral Coupling Enabled Topside Only Dual-side Testing Of Tsv Die Attached To Package Substrate
App 20110304349 - Stillman; Daniel Joseph ;   et al.
2011-12-15
Through Carrier Dual Side Loop-back Testing Of Tsv Die After Die Attach To Substrate
App 20110298488 - Stillman; Daniel Joseph ;   et al.
2011-12-08
Semiconductor wafer with ditched scribe street
App 20050266661 - Li, Lei ;   et al.
2005-12-01
Semiconductor packages and methods for manufacturing such semiconductor packages
Grant 6,768,212 - Karashima , et al. July 27, 2
2004-07-27
Semiconductor packages and methods for manufacturing such semiconductor packages
App 20030137033 - Karashima, Akira ;   et al.
2003-07-24
Package for printhead chip
App 20030090558 - Coyle, Anthony L. ;   et al.
2003-05-15

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