Patent | Date |
---|
Early analysis and mitigation of self-heating in design flows Grant 9,990,454 - Dhanwada , et al. June 5, 2 | 2018-06-05 |
Early Analysis And Mitigation Of Self-heating In Design Flows App 20170351785 - Dhanwada; Nagashyamala R. ;   et al. | 2017-12-07 |
Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications Grant 9,552,455 - Poindexter , et al. January 24, 2 | 2017-01-24 |
Method for an Efficient Modeling of the Impact of Device-Level Self-Heating on Electromigration Limited Current Specifications App 20160224717 - Poindexter; Daniel J. ;   et al. | 2016-08-04 |
Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design Grant 9,104,832 - Barwin, III , et al. August 11, 2 | 2015-08-11 |
Identifying And Mitigating Electromigration Failures In Signal Nets Of An Integrated Circuit Chip Design App 20150205906 - Barwin, III; John E. ;   et al. | 2015-07-23 |
Power grid generation through modification of an initial power grid based on power grid analysis Grant 8,914,765 - Sigal , et al. December 16, 2 | 2014-12-16 |
Power Grid Design For Integrated Circuits App 20140201695 - Sigal; Leon J. ;   et al. | 2014-07-17 |
Apparatus and method for hardening latches in SOI CMOS devices Grant 8,354,858 - Cannon , et al. January 15, 2 | 2013-01-15 |
Apparatus And Method For Hardening Latches In Soi Cmos Devices App 20110102042 - Cannon; Ethan H. ;   et al. | 2011-05-05 |
Apparatus and method for hardening latches in SOI CMOS devices Grant 7,888,959 - Cannon , et al. February 15, 2 | 2011-02-15 |
Low-power multi-output local clock buffer Grant 7,589,565 - Sigal , et al. September 15, 2 | 2009-09-15 |
Low-power Multi-output Local Clock Buffer App 20090199038 - Sigal; Leon J. ;   et al. | 2009-08-06 |
Independent migration of hierarchical designs with methods of finding and fixing opens during migration Grant 7,568,173 - Gernhoefer , et al. July 28, 2 | 2009-07-28 |
Apparatus And Method For Hardening Latches In Soi Cmos Devices App 20090134925 - Cannon; Ethan H. ;   et al. | 2009-05-28 |
Independent Migration Of Hierarchical Designs With Methods Of Finding And Fixing Opens During Migration App 20080313581 - Gernhoefer; Veit ;   et al. | 2008-12-18 |
Hierarchical scalable high resolution digital programmable delay circuit Grant 7,456,671 - Hwang , et al. November 25, 2 | 2008-11-25 |
Hierarchical Scalable High Resolution Digital Programmable Delay Circuit App 20080169857 - Hwang; Charlie C ;   et al. | 2008-07-17 |
System and method for topology selection to minimize leakage power during synthesis Grant 7,100,144 - Jacobson , et al. August 29, 2 | 2006-08-29 |
System and method for topology selection to minimize leakage power during synthesis App 20050125761 - Jacobson, Hans M. ;   et al. | 2005-06-09 |
Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design Grant 6,629,298 - Camporese , et al. September 30, 2 | 2003-09-30 |
Dynamic and preset static multiplexer in front of latch circuit for use in static circuits Grant 5,543,731 - Sigal , et al. August 6, 1 | 1996-08-06 |
Two-phase overlapping clocking technique for digital dynamic circuits Grant 5,504,441 - Sigal April 2, 1 | 1996-04-02 |
VLSI clocking system using both overlapping and non-overlapping clocks Grant 5,124,572 - Mason , et al. June 23, 1 | 1992-06-23 |