Siers; Scott E.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Siers; Scott E..The latest application filed is for "processor power consumption control and voltage drop via micro-architectural bandwidth throttling".
- Siers; Scott E. - Elk Grove CA
| Patent | Date |
|---|---|
| Memory cell write Grant 8,345,491 - Damaraju , et al. January 1, 2 | 2013-01-01 |
| Processor Power Consumption Control And Voltage Drop Via Micro-architectural Bandwidth Throttling App 20120210105 - Jahagirdar; Sanjeev ; et al. | 2012-08-16 |
| Memory Cell Write App 20120039135 - Damaraju; Satish K. ; et al. | 2012-02-16 |
| Memory cell write Grant 8,050,116 - Damaraju , et al. November 1, 2 | 2011-11-01 |
| Processor power consumption control and voltage drop via micro-architectural bandwidth throttling Grant 8,028,181 - Jahagirdar , et al. September 27, 2 | 2011-09-27 |
| Memory Cell Write App 20110069566 - Damaraju; Satish K. ; et al. | 2011-03-24 |
| Processor power consumption control and voltage drop via micro-architectural bandwidth throttling App 20100077232 - Jahagirdar; Sanjeev ; et al. | 2010-03-25 |
| Methods and apparatus for address generation in processors Grant 7,269,711 - Patel , et al. September 11, 2 | 2007-09-11 |
| Methods and apparatus for address generation in processors App 20050144423 - Patel, Rajesh B. ; et al. | 2005-06-30 |
| Dual rail time borrowing multiplexer Grant 6,891,400 - Yeager , et al. May 10, 2 | 2005-05-10 |
| Dual rail time borrowing multiplexer App 20040217779 - Yeager, Hans L. ; et al. | 2004-11-04 |
| Domino circuit topology Grant 6,784,695 - Yeager , et al. August 31, 2 | 2004-08-31 |
| Domino Circuit Topology App 20040164768 - Yeager, Hans L. ; et al. | 2004-08-26 |
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