Sienko; Matthew D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sienko; Matthew D..The latest application filed is for "split capacitors scheme for suppressing overshoot voltage glitches in class d amplifier output stage".

Company Profile

0.12.9

Sienko; Matthew D. - San Diego CA US
Sienko; Matthew D. - La Jolla CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Overcurrent protection for class D power amplifier Grant 9,088,251 - Fei , et al. July 21, 2	2015-07-21
Load current sensing Grant 8,963,634 - Srivastava , et al. February 24, 2	2015-02-24
Split capacitors scheme for suppressing overshoot voltage glitches in class D amplifier output stage Grant 8,947,163 - Huang , et al. February 3, 2	2015-02-03
Digital to-analog converter circuitry with weighted resistance elements Grant 8,860,597 - Sienko October 14, 2	2014-10-14
Split Capacitors Scheme for Suppressing Overshoot Voltage Glitches in Class D Amplifier Output Stage App 20130293298 - Huang; Chenling ; et al.	2013-11-07
Overcurrent Protection for Class D Power Amplifier App 20130285744 - Fei; Haibo ; et al.	2013-10-31
Load Current Sensing App 20130223649 - Srivastava; Ankit ; et al.	2013-08-29
Digital-to-analog Converter Circuitry With Weighted Resistance Elements App 20130169461 - Sienko; Matthew D.	2013-07-04
Apparatus and methods for digital-to-analog conversion with vector quantization Grant 8,098,718 - Sienko , et al. January 17, 2	2012-01-17
Operational amplifier and method for amplifying a signal with shared compensation components Grant 7,884,672 - Cetin , et al. February 8, 2	2011-02-08
Apparatus And Methods For Digital-to-analog Conversion With Vector Quantization App 20110002264 - Sienko; Matthew D. ; et al.	2011-01-06
Universal serial bus (USB) driver circuit, system, and method Grant 7,595,674 - Cetin , et al. September 29, 2	2009-09-29
Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up Grant 7,560,987 - Cetin , et al. July 14, 2	2009-07-14

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