SIEGEL; JOSEPH R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for SIEGEL; JOSEPH R..The latest application filed is for "interposer transmission line using multiple metal layers".

Company Profile

0.9.11

SIEGEL; JOSEPH R. - BOXBOROUGH MA
Siegel; Joseph R. - Brookline MA US
Siegel; Joseph R. - Shrewsbury MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interposer Transmission Line Using Multiple Metal Layers App 20180130780 - GONZALES; DEAN ; et al.	2018-05-10
Interposer with beyond reticle field conductor pads Grant 9,806,014 - Alfano , et al. October 31, 2	2017-10-31
Interposer With Beyond Reticle Field Conductor Pads App 20170213787 - Alfano; Michael S. ; et al.	2017-07-27
Via Capacitor App 20170092712 - Siegel; Joseph R. ; et al.	2017-03-30
Fault tolerant scannable glitch latch Grant 8,850,278 - Gillespie , et al. September 30, 2	2014-09-30
Fault Tolerant Scannable Glitch Latch App 20120166899 - Gillespie; Kevin M. ; et al.	2012-06-28
Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops Grant 7,000,164 - Siegel , et al. February 14, 2	2006-02-14
Scanable R-S glitch latch for dynamic circuits Grant 6,907,556 - Siegel June 14, 2	2005-06-14
Single edge-triggered flip-flop design with asynchronous programmable reset App 20040187086 - Trivedi, Pradeep R. ; et al.	2004-09-23
Dual edge-triggered flip-flop design with asynchronous programmable reset Grant 6,720,813 - Yee , et al. April 13, 2	2004-04-13
System and method for automatic generation of an at-speed counter Grant 6,700,946 - Zarrineh , et al. March 2, 2	2004-03-02
System and method for automatic generation of an at-speed counter App 20030152188 - Zarrineh, Kamran ; et al.	2003-08-14
Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip floops App 20030145264 - Siegel, Joseph R. ; et al.	2003-07-31
Scanable R-S glitch latch for dynamic circuits App 20030145265 - Siegel, Joseph R.	2003-07-31
Memory array with common word line Grant 6,594,194 - Gold , et al. July 15, 2	2003-07-15
Method and system for banking register file memory arrays App 20030012072 - Gold, Spencer M. ; et al.	2003-01-16

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