Siegel; Joseph
Patent Applications and Registrations
Patent applications and USPTO patent grants for Siegel; Joseph.The latest application filed is for "semiconductor chip with thermal interface tape".
- Siegel; Joseph - Brookline MA US
- Siegel; Joseph - Shrewsbury MA
| Patent | Date |
|---|---|
| Semiconductor chip with thermal interface tape Grant 9,627,281 - Prejean , et al. April 18, 2 | 2017-04-18 |
| Die stacking, testing and packaging for yield Grant 8,451,014 - Black , et al. May 28, 2 | 2013-05-28 |
| Semiconductor Chip With Thermal Interface Tape App 20120043539 - Prejean; Seth ; et al. | 2012-02-23 |
| Method and system for monitoring and profiling an integrated circuit die temperature Grant 6,996,491 - Gold , et al. February 7, 2 | 2006-02-07 |
| Implementation of an assertion check in ATPG models Grant 6,785,855 - Zhang , et al. August 31, 2 | 2004-08-31 |
| Method and system for monitoring and profiling an integrated circuit die temperature App 20030158697 - Gold, Spencer M. ; et al. | 2003-08-21 |
| Scannable latch for a dynamic circuit Grant 6,570,407 - Sugisawa , et al. May 27, 2 | 2003-05-27 |
| Implementation of an assertion check in ATPG models App 20030093734 - Zhang, Aiteen ; et al. | 2003-05-15 |
| Automated decoupling capacitor insertion App 20020144217 - Lin, Chen Li ; et al. | 2002-10-03 |
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