Sidiropoulos; Stefanos

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sidiropoulos; Stefanos.The latest application filed is for "memory component with pattern register circuitry to provide data patterns for calibration".

Company Profile

7.101.70

Sidiropoulos; Stefanos - Palo Alto CA
- Palo Alto CA US
Sidiropoulos; Stefanos - Stanford CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Differential clock skew detector Grant 11,341,002 - Izad , et al. May 24, 2	2022-05-24
Memory component with pattern register circuitry to provide data patterns for calibration Grant 11,232,827 - Hampel , et al. January 25, 2	2022-01-25
Memory Component With Pattern Register Circuitry To Provide Data Patterns For Calibration App 20210098048 - HAMPEL; Craig E. ; et al.	2021-04-01
Memory component with pattern register circuitry to provide data patterns for calibration Grant 10,811,080 - Hampel , et al. October 20, 2	2020-10-20
Memory Component With Pattern Register Circuitry To Provide Data Patterns For Calibration App 20190214074 - HAMPEL; Craig E. ; et al.	2019-07-11
Flash memory controller with calibrated data communication Grant 10,310,999 - Zerbe , et al.	2019-06-04
Memory component with pattern register circuitry to provide data patterns for calibration Grant 10,192,609 - Hampel , et al. Ja	2019-01-29
Multi-PAM output driver with distortion compensation Grant 9,998,305 - Zerbe , et al. June 12, 2	2018-06-12
Flash Memory Controller With Calibrated Data Communication App 20180095916 - Zerbe; Jared LeVan ; et al.	2018-04-05
Timing-modulated side channel Grant 9,917,655 - Kasapi , et al. March 13, 2	2018-03-13
Memory Component With Pattern Register Circuitry To Provide Data Patterns For Calibration App 20180012643 - Hampel; Craig E. ; et al.	2018-01-11
Memory controller that calibrates a transmit timing offset Grant 9,785,589 - Zerbe , et al. October 10, 2	2017-10-10
Multi-PAM Output Driver with Distortion Compensation App 20170222845 - Zerbe; Jared L. ; et al.	2017-08-03
Memory component with pattern register circuitry to provide data patterns for calibration Grant 9,721,642 - Hampel , et al. August 1, 2	2017-08-01
Flash Memory Controller With Calibrated Data Communication App 20170031854 - Zerbe; Jared LeVan ; et al.	2017-02-02
Adaptable rate transceiver Grant 9,515,694 - Sidiropoulos December 6, 2	2016-12-06
Memory Component With Pattern Register Circuitry To Provide Data Patterns For Calibration App 20160260469 - Hampel; Craig E. ; et al.	2016-09-08
Flash memory controller with calibrated data communication Grant 9,405,678 - Zerbe , et al. August 2, 2	2016-08-02
Memory component with pattern register circuitry to provide data patterns for calibration Grant 9,367,248 - Hampel , et al. June 14, 2	2016-06-14
Flash Memory Controller With Calibrated Data Communication App 20160011973 - Zerbe; Jared LeVan ; et al.	2016-01-14
Memory system with calibrated data communication Grant 9,164,933 - Zerbe , et al. October 20, 2	2015-10-20
Memory Component With Pattern Register Circuitry To Provide Data Patterns For Calibration App 20150286408 - Hampel; Craig E. ; et al.	2015-10-08
Memory component with pattern register circuitry to provide data patterns for calibration Grant 9,123,433 - Hampel , et al. September 1, 2	2015-09-01
Memory component with pattern register circuitry to provide data patterns for calibration Grant 9,099,194 - Hampel , et al. August 4, 2	2015-08-04
Multi-value logic signaling in multi-functional circuits Grant 9,094,020 - Loinaz , et al. July 28, 2	2015-07-28
Memory System with Calibrated Data Communication App 20150169478 - Zerbe; Jared LeVan ; et al.	2015-06-18
Systems, circuits and methods for filtering signals to compensate for channel effects Grant 8,948,331 - Cirit , et al. February 3, 2	2015-02-03
Memory controller with circuitry to set memory device-specific reference voltages Grant 8,948,212 - Zerbe , et al. February 3, 2	2015-02-03
Multiphase Receiver with Equalization Circuitry App 20140286389 - Zerbe; Jared L. ; et al.	2014-09-25
Memory System with Calibrated Data Communication App 20140229667 - Zerbe; Jared LeVan ; et al.	2014-08-14
Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation Grant 8,667,038 - Sidiropoulos March 4, 2	2014-03-04
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration App 20140032830 - Hampel; Craig E. ; et al.	2014-01-30
Repeate architecture with single clock multiplier unit Grant 8,638,896 - Liu , et al. January 28, 2	2014-01-28
Multiphase receiver with equalization circuitry Grant 8,634,452 - Zerbe , et al. January 21, 2	2014-01-21
Memory system with calibrated data communication Grant 8,630,317 - Zerbe , et al. January 14, 2	2014-01-14
Systems, circuits, and methods for a sigma-delta based time to digital converter Grant 08618967 -	2013-12-31
Systems, circuits, and methods for a sigma-delta based time to digital converter Grant 8,618,967 - Nikaeen , et al. December 31, 2	2013-12-31
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration App 20130346685 - Hampel; Craig E. ; et al.	2013-12-26
Methods and apparatus for clock and data recovery using transmission lines Grant 8,599,983 - Sidiropoulos , et al. December 3, 2	2013-12-03
Multi-Value Logic Signaling in Multi-Functional Circuits App 20130285736 - LOINAZ; Marc ; et al.	2013-10-31
Systems, Circuits and Methods for Filtering Signals to Compensate for Channel Effects App 20130287409 - CIRIT; Halil ; et al.	2013-10-31
Systems, circuits, and methods for a digital frequency synthesizer Grant 8,552,767 - Nikaeen , et al. October 8, 2	2013-10-08
Systems, Circuits, And Methods For A Digital Frequency Synthesizer App 20130257485 - Nikaeen; Parastoo ; et al.	2013-10-03
Systems, Circuits, and Methods for a Sigma-Delta Based Time to Digital Converter App 20130257494 - Nikaeen; Parastoo ; et al.	2013-10-03
Systems, circuits and methods for filtering signals to compensate for channel effects Grant 8,537,949 - Cirit , et al. September 17, 2	2013-09-17
Multi-value logic signaling in multi-functional circuits Grant 8,520,744 - Loinaz , et al. August 27, 2	2013-08-27
Methods and apparatus for frequency synthesis with feedback interpolation Grant 8,433,018 - Sidiropoulos , et al. April 30, 2	2013-04-30
Apparatus and method for controlling a master/slave system via master device synchronization Grant 8,428,210 - Sidiropoulos April 23, 2	2013-04-23
Systems, methods, and circuits for driving large off-chip loads Grant 8,369,369 - Sidiropoulos , et al. February 5, 2	2013-02-05
Multiphase receiver with equalization circuitry App 20130010855 - Zerbe; Jared L. ; et al.	2013-01-10
Method and apparatus for adjusting the performance of a synchronous memory system Grant 8,296,540 - Garlepp , et al. October 23, 2	2012-10-23
Methods And Apparatus For Clock And Data Recovery Using Transmission Lines App 20120230450 - Sidiropoulos; Stefanos ; et al.	2012-09-13
Memory System with Calibrated Data Communication App 20120204054 - Zerbe; Jared LeVan ; et al.	2012-08-09
Integrating receiver with precharge circuitry Grant 8,199,859 - Zerbe , et al. June 12, 2	2012-06-12
Memory system with calibrated data communication Grant 8,170,067 - Zerbe , et al. May 1, 2	2012-05-01
Methods and apparatus for clock and data recovery using transmission lines Grant 8,155,236 - Sidiropoulos , et al. April 10, 2	2012-04-10
Methods and apparatus for clock and data recovery using transmission lines Grant 8,102,936 - Sidiropoulos , et al. January 24, 2	2012-01-24
Multi-Value Logic Signaling in Multi-Functional Circuits App 20110228860 - Loinaz; Marc ; et al.	2011-09-22
Repeater Architecture with Single Clock Multiplier Unit App 20110228889 - Liu; Dean ; et al.	2011-09-22
Integrating Receiver With Precharge Circuitry App 20110140741 - Zerbe; Jared L. ; et al.	2011-06-16
Systems, Methods, and Circuits for Driving Large Off-Chip Loads App 20110103417 - Sidiropoulos; Stefanos ; et al.	2011-05-05
Methods and circuits for driving large off-chip loads Grant 7,885,300 - Sidiropoulos , et al. February 8, 2	2011-02-08
Memory device receiver Grant 7,859,436 - Werner , et al. December 28, 2	2010-12-28
Programmable delay clock buffer Grant 7,849,348 - Sidiropoulos , et al. December 7, 2	2010-12-07
Multiphase receiver with equalization Grant 7,809,088 - Zerbe , et al. October 5, 2	2010-10-05
Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization App 20100146172 - Sidiropoulos; Stefanos	2010-06-10
Low Latency Multi-Level Communication Interface App 20100134153 - Zerbe; Jared L. ; et al.	2010-06-03
Apparatus and method for controlling a master/slave system via master device synchronization Grant 7,702,057 - Sidiropoulos April 20, 2	2010-04-20
Memory System with Calibrated Data Communication App 20090327789 - Zerbe; Jared LeVan ; et al.	2009-12-31
System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices App 20090319719 - Perego; Richard E. ; et al.	2009-12-24
Low latency multi-level communication interface Grant 7,626,442 - Zerbe , et al. December 1, 2	2009-12-01
Master device with time domains for slave devices in synchronous memory system Grant 7,570,726 - Sidiropoulos August 4, 2	2009-08-04
Slave device with synchronous interface for use in synchronous memory system Grant 7,548,601 - Sidiropoulos June 16, 2	2009-06-16
Calibrated data communication system and method Grant 7,535,933 - Zerbe , et al. May 19, 2	2009-05-19
Methods and apparatus for clock and data recovery using a single source Grant 7,532,697 - Sidiropoulos , et al. May 12, 2	2009-05-12
System having a controller device, a buffer device and a plurality of memory devices Grant 7,523,248 - Perego , et al. April 21, 2	2009-04-21
Memory Device Receiver App 20090097338 - Werner; Carl ; et al.	2009-04-16
Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization App 20090045854 - Sidiropoulos; Stefanos	2009-02-19
Slave device with calibration signal generator for synchronous memory system Grant 7,489,756 - Sidiropoulos February 10, 2	2009-02-10
Apparatus and method for controlling a master/slave system via master device synchronization Grant 7,466,784 - Sidiropoulos December 16, 2	2008-12-16
Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals Grant 7,456,778 - Werner , et al. November 25, 2	2008-11-25
Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation Grant 7,443,215 - Sidiropoulos October 28, 2	2008-10-28
Methods and Apparatus for Frequency Synthesis with Feedback Interpolation App 20080260071 - Sidiropoulos; Stefanos ; et al.	2008-10-23
Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation Grant 7,436,229 - Sidiropoulos , et al. October 14, 2	2008-10-14
Methods and apparatus for frequency synthesis with feedback interpolation Grant 7,432,750 - Sidiropoulos , et al. October 7, 2	2008-10-07
Method And Apparatus For Adjusting The Performance Of A Synchronous Memory System App 20080162759 - Garlepp; Bruno Werner ; et al.	2008-07-03
System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices App 20080109596 - Perego; Richard E. ; et al.	2008-05-08
Methods And Apparatus For Clock And Data Recovery Using Transmission Lines App 20080049850 - Sidiropoulos; Stefanos ; et al.	2008-02-28
Methods and Apparatus for Minimizing Jitter in a Clock Synthesis Circuit that Uses Feedback Interpolation App 20080048734 - Sidiropoulos; Stefanos ; et al.	2008-02-28
Method and apparatus for adjusting the performance of a synchronous memory system Grant 7,337,294 - Garlepp , et al. February 26, 2	2008-02-26
Methods and apparatus for generating multiple clocks using feedback interpolation Grant 7,323,916 - Sidiropoulos , et al. January 29, 2	2008-01-29
Master Device with Time Domains for Slave Devices in Synchronous Memory System App 20080013662 - Sidiropoulos; Stefanos	2008-01-17
System having a controller device, a buffer device and a plurality of memory devices Grant 7,320,047 - Perego , et al. January 15, 2	2008-01-15
Slave Device with Calibration Signal Generator for Synchronous Memory System App 20070258554 - Sidiropoulos; Stefanos	2007-11-08
Slave Device with Synchronous Interface for Use in Synchronous Memory System App 20070258555 - Sidiropoulos; Stefanos	2007-11-08
Memory module having an integrated circuit buffer device Grant 7,206,897 - Perego , et al. April 17, 2	2007-04-17
Integrated circuit buffer device Grant 7,206,896 - Perego , et al. April 17, 2	2007-04-17
Method And Apparatus For Adjusting The Performance Of A Synchronous Memory System App 20070083700 - Garlepp; Bruno Werner ; et al.	2007-04-12
Buffer device and method of operation in a buffer device Grant 7,200,710 - Perego , et al. April 3, 2	2007-04-03
Method and apparatus for adjusting the performance of a synchronous memory system Grant 7,149,856 - Garlepp , et al. December 12, 2	2006-12-12
Low latency multi-level communication interface Grant 7,124,221 - Zerbe , et al. October 17, 2	2006-10-17
Reducing coupled noise in pseudo-differential signaling systems Grant 7,099,395 - Sidiropoulos , et al. August 29, 2	2006-08-29
Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals App 20060186915 - Werner; Carl ; et al.	2006-08-24
Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals Grant 7,093,145 - Werner , et al. August 15, 2	2006-08-15
Low latency multi-level communication interface App 20060170453 - Zerbe; Jared L. ; et al.	2006-08-03
Integrated circuit buffer device Grant 7,062,597 - Perego , et al. June 13, 2	2006-06-13
Calibrated data communication system and method App 20060120409 - Zerbe; Jared LeVan ; et al.	2006-06-08
Integrated circuit buffer device Grant 7,051,151 - Perego , et al. May 23, 2	2006-05-23
Calibrated data communication system and method Grant 7,042,914 - Zerbe , et al. May 9, 2	2006-05-09
Integrated Circuit Buffer Device App 20060067141 - Perego; Richard E. ; et al.	2006-03-30
System featuring a master device, a buffer device and a plurality of integrated circuit memory devices Grant 7,017,002 - Perego , et al. March 21, 2	2006-03-21
Integrated circuit device having I/O structures with reduced input loss Grant 7,012,330 - Sidiropoulos , et al. March 14, 2	2006-03-14
System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices Grant 7,010,642 - Perego , et al. March 7, 2	2006-03-07
System featuring memory modules that include an integrated circuit buffer devices Grant 7,003,618 - Perego , et al. February 21, 2	2006-02-21
System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices Grant 7,000,062 - Perego , et al. February 14, 2	2006-02-14
System and method for aligning internal transmit and receive clocks Grant 6,987,823 - Stark , et al. January 17, 2	2006-01-17
Apparatus and method for generating clock signals App 20050265117 - Lau, Benedict C. ; et al.	2005-12-01
Apparatus and method for generating clock signals Grant 6,954,095 - Lau , et al. October 11, 2	2005-10-11
System and method for aligning internal transmit and receive clocks App 20050220235 - Stark, Donald C. ; et al.	2005-10-06
Buffer device and method of operation in a buffer device App 20050223179 - Perego, Richard E. ; et al.	2005-10-06
Integrated circuit with timing adjustment mechanism and method Grant 6,950,956 - Zerbe , et al. September 27, 2	2005-09-27
System having a controller device, a buffer device and a plurality of memory devices App 20050207255 - Perego, Richard E. ; et al.	2005-09-22
Memory module having an integrated circuit buffer device App 20050210196 - perego, Richard E. ; et al.	2005-09-22
Integrated circuit buffer device App 20050193163 - Perego, Richard E. ; et al.	2005-09-01
Clock alignment circuit having a self regulating voltage supply Grant 6,928,128 - Sidiropoulos August 9, 2	2005-08-09
System featuring memory modules that include an integrated circuit buffer devices App 20050156934 - Perego, Richard E. ; et al.	2005-07-21
System having a plurality of integrated circuit buffer devices App 20050149662 - Perego, Richard E. ; et al.	2005-07-07
Apparatus and method for controlling a master/slave system via master device synchronization App 20050057292 - Sidiropoulos, Stefanos	2005-03-17
Method of operating a memory system including an integrated circuit buffer device App 20050041504 - Perego, Richard E. ; et al.	2005-02-24
Memory system including an integrated circuit buffer device App 20050044303 - Perego, Richard E. ; et al.	2005-02-24
Method and apparatus for calibrating a multi-level current mode driver App 20050005179 - Werner, Carl ; et al.	2005-01-06
Apparatus and method for controlling a master/slave system via master device synchronization Grant 6,839,393 - Sidiropoulos January 4, 2	2005-01-04
Dual loop phase lock loops using dual voltage supply regulators Grant 6,809,600 - Chang , et al. October 26, 2	2004-10-26
Apparatus and method for generating clock signals App 20040174195 - Lau, Benedict C. ; et al.	2004-09-09
Method and apparatus for adjusting the performance of a synchronous memory system App 20040168036 - Garlepp, Bruno Werner ; et al.	2004-08-26
Method and apparatus for calibrating a multi-level current mode driver Grant 6,772,351 - Werner , et al. August 3, 2	2004-08-03
Integrated circuit with timing adjustment mechanism and method App 20040098634 - Zerbe, Jared LeVan ; et al.	2004-05-20
Apparatus and method for generating clock signals Grant 6,731,148 - Lau , et al. May 4, 2	2004-05-04
Calibrated data communication system and method App 20040076192 - Zerbe, Jared LeVan ; et al.	2004-04-22
Bus system optimization Grant 6,643,787 - Zerbe , et al. November 4, 2	2003-11-04
Current-mode bus line driver having increased output impedance Grant 6,618,786 - Sidiropoulos , et al. September 9, 2	2003-09-09
Reconfigurable dual-mode multiple stage operational amplifiers App 20030122621 - Sidiropoulos, Stefanos ; et al.	2003-07-03
Dual loop phase lock loops using dual voltage supply regulators App 20030107418 - Chang, Kun-Yung Ken ; et al.	2003-06-12
Duty cycle integrator with tracking common mode feedback control Grant 6,573,779 - Sidiropoulos , et al. June 3, 2	2003-06-03
Synchronous memory device having a temperature register Grant 6,553,452 - Garlepp , et al. April 22, 2	2003-04-22
Memory system including a point-to-point linked memory subsystem App 20030061447 - Perego, Richard E. ; et al.	2003-03-27
Method and apparatus for adjusting the performance of a synchronous memory system Grant 6,513,103 - Garlepp , et al. January 28, 2	2003-01-28
Memory system including a point-to-point linked memory subsystem Grant 6,502,161 - Perego , et al. December 31, 2	2002-12-31
Duty cycle integrator with tracking common mode feedback control App 20020175739 - Sidiropoulos, Stefanos ; et al.	2002-11-28
Reconfigurable dual-mode multiple stage operational amplifiers App 20020171487 - Sidiropoulos, Stefanos ; et al.	2002-11-21
Apparatus and method for generating multiple clock signals from a single loop circuit Grant 6,469,555 - Lau , et al. October 22, 2	2002-10-22
Apparatus and method for generating clock signals App 20020140473 - Lau, Benedict C. ; et al.	2002-10-03
Apparatus and method for edge based duty cycle conversion Grant 6,448,828 - Stark , et al. September 10, 2	2002-09-10
Method and apparatus for adjusting the performance of a synchronous memory system App 20020087820 - Garlepp, Bruno Werner ; et al.	2002-07-04
Apparatus and method for edge based duty cycle conversion App 20020017936 - Stark, Donald C. ; et al.	2002-02-14
Apparatus and method for edge based duty cycle conversion Grant 6,323,706 - Stark , et al. November 27, 2	2001-11-27
Apparatus and method for detecting two data bits per clock edge Grant 6,232,796 - Batra , et al. May 15, 2	2001-05-15
Variable delay element Grant 6,133,773 - Garlepp , et al. October 17, 2	2000-10-17