Shutler; William F.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shutler; William F..The latest application filed is for "jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules".

Company Profile

0.6.4

Shutler; William F. - Wappingers Falls NY
Shutler; William F. - Wappinger Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules Grant 6,974,722 - Daves , et al. December 13, 2	2005-12-13
Jogging Structure For Wiring Translation Between Grids With Non-integral Pitch Ratios In Chip Carrier Modules App 20040188823 - Daves, Glenn G. ; et al.	2004-09-30
Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules Grant 6,762,489 - Daves , et al. July 13, 2	2004-07-13
Structure and method for wiring translation between grids with non-integral pitch ratios in chip carrier modules App 20030094687 - Daves, Glenn G. ; et al.	2003-05-22
High Bandwidth 3d Memory Packaging Technique App 20020117741 - Beausoleil, William F. ; et al.	2002-08-29
Novel MCM -MLC technology App 20010046125 - Rehm, Simone ; et al.	2001-11-29
Two-stage power noise filter with on and off chip capacitors Grant 6,043,724 - Frech , et al. March 28, 2	2000-03-28
Multilayer module with thinfilm redistribution area Grant 5,914,533 - Frech , et al. June 22, 1	1999-06-22
Integrated thermoelectric cooling Grant 5,032,897 - Mansuria , et al. July 16, 1	1991-07-16
Intermediate memory array with a parallel port and a buffered serial port Grant 4,718,039 - Aichelmann, Jr. , et al. January 5, 1	1988-01-05

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