SHUMARAYEV; Sergey Yuryevich

Patent Applications and Registrations

Patent applications and USPTO patent grants for SHUMARAYEV; Sergey Yuryevich.The latest application filed is for "off-package high density, high bandwidth memory access using optical links".

Company Profile

0.30.12

SHUMARAYEV; Sergey Yuryevich - Los Altos Hills CA
Shumarayev; Sergey Yuryevich - San Leandro CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Off-package High Density, High Bandwidth Memory Access Using Optical Links App 20220092016 - KUMASHIKAR; Mahesh K. ; et al.	2022-03-24
Integrated circuit device with field programmable optical array Grant 10,212,498 - Li , et al. Feb	2019-02-19
Integrated circuit device with field programmable optical array Grant 9,608,728 - Li , et al. March 28, 2	2017-03-28
Integrated circuit system with dynamic decoupling and method of manufacture thereof Grant 9,153,572 - Oh , et al. October 6, 2	2015-10-06
High-speed data reception circuitry and methods Grant 8,743,943 - Shumarayev , et al. June 3, 2	2014-06-03
Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry Grant 8,649,461 - Shumarayev February 11, 2	2014-02-11
Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits Grant 8,570,197 - Nguyen , et al. October 29, 2	2013-10-29
Decision feedback equalization for variable input amplitude Grant 8,416,845 - Wong , et al. April 9, 2	2013-04-09
Receiver equalizer circuitry having wide data rate and input common mode voltage ranges Grant 8,222,967 - Raman , et al. July 17, 2	2012-07-17
Wide range and dynamically reconfigurable clock data recovery architecture Grant 8,189,729 - Hoang , et al. May 29, 2	2012-05-29
Lane-to-lane Skew Reduction In Multi-channel, High-speed, Transceiver Circuitry App 20120063539 - Shumarayev; Sergey Yuryevich	2012-03-15
Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry Grant 8,081,706 - Shumarayev December 20, 2	2011-12-20
Serializer Circuitry For High-speed Serial Data Transmitters On Programmable Logic Device Integrated Circuits App 20110068845 - Nguyen; Toan Thanh ; et al.	2011-03-24
Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits Grant 7,848,318 - Nguyen , et al. December 7, 2	2010-12-07
Half-rate DFE with duplicate path for high data-rate operation Grant 7,782,935 - Wong , et al. August 24, 2	2010-08-24
Programmable logic enabled dynamic offset cancellation Grant 7,724,079 - Shumarayev May 25, 2	2010-05-25
High-speed serial data receiver architecture Grant 7,702,011 - Tran , et al. April 20, 2	2010-04-20
Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits Grant 7,659,838 - Nguyen , et al. February 9, 2	2010-02-09
Multi-channel communication circuitry for programmable logic device integrated circuits and the like Grant 7,656,187 - Tran , et al. February 2, 2	2010-02-02
Power supply circuitry for data signal transceivers on integrated circuits Grant 7,639,993 - Shumarayev , et al. December 29, 2	2009-12-29
High-speed serial data transmitter architecture Grant 7,557,615 - Tran , et al. July 7, 2	2009-07-07
Programmable transceivers that are able to operate over wide frequency ranges Grant 7,539,278 - Shumarayev , et al. May 26, 2	2009-05-26
High-speed serial data transmitter architecture Grant 7,355,449 - Tran , et al. April 8, 2	2008-04-08
Dynamic bias circuit Grant 7,324,031 - Lai , et al. January 29, 2	2008-01-29
Programmable logic enabled dynamic offset cancellation Grant 7,321,259 - Shumarayev January 22, 2	2008-01-22
Modular buffering circuitry for multi-channel transceiver clock and other signals Grant 7,304,507 - Tran , et al. December 4, 2	2007-12-04
Equalization circuit cells with higher-order response characteristics Grant 7,279,924 - Shumarayev October 9, 2	2007-10-09
Clock circuitry for programmable logic devices Grant 7,276,936 - Hoang , et al. October 2, 2	2007-10-02
Modular interconnect circuitry for multi-channel transceiver clock signals Grant 7,276,937 - Hoang , et al. October 2, 2	2007-10-02
Programmable transceivers that are able to operate over wide frequency ranges App 20070127616 - Shumarayev; Sergey Yuryevich ; et al.	2007-06-07
Multi-channel communication circuitry for programmable logic device integrated circuits and the like App 20070058618 - Tran; Thungoc ; et al.	2007-03-15
Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry App 20070047667 - Shumarayev; Sergey Yuryevich	2007-03-01
High-speed serial data receiver architecture App 20070041455 - Tran; Thungoc M. ; et al.	2007-02-22
Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits App 20070043991 - Nguyen; Toan Thanh ; et al.	2007-02-22
Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits App 20070030184 - Nguyen; Toan Thanh ; et al.	2007-02-08
High-speed data reception circuitry and methods App 20070025436 - Shumarayev; Sergey Yuryevich ; et al.	2007-02-01
Modular interconnect circuitry for multi-channel transceiver clock signals App 20070018863 - Hoang; Tim Tri ; et al.	2007-01-25
Methods and apparatus to DC couple LVDS driver to CML levels App 20060220681 - Wong; Wilson ; et al.	2006-10-05

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