Shonai; Toru

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shonai; Toru.The latest application filed is for "system and method for managing data processing devices".

Company Profile

0.7.7

Shonai; Toru - Hachioji JP
Shonai; Toru - Kodaira JP
Shonai, Toru - Tokyo JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Computer forming logical partitions Grant 7,281,249 - Tarui , et al. October 9, 2	2007-10-09
Shared memory multiprocessor system Grant 7,206,818 - Okochi , et al. April 17, 2	2007-04-17
Computer resource allocating method Grant 7,062,559 - Yoshimura , et al. June 13, 2	2006-06-13
Shared memory multiprocessor performing cache coherence control and node controller therefor Grant 6,874,053 - Yasuda , et al. March 29, 2	2005-03-29
System and method for managing data processing devices App 20040177143 - Maciel, Frederico Buchholz ; et al.	2004-09-09
Node controller for performing cache coherence control and memory-shared multiprocessor system Grant 6,789,173 - Tanaka , et al. September 7, 2	2004-09-07
Shared memory multiprocessor performing cache coherence control and node controller therefor App 20040054855 - Yasuda, Yoshiko ; et al.	2004-03-18
Shared memory multiprocessor system App 20040024839 - Okochi, Toshio ; et al.	2004-02-05
Shared memory multiprocessor performing cache coherence control and node controller therefor Grant 6,636,926 - Yasuda , et al. October 21, 2	2003-10-21
Computer resource allocating method App 20030069972 - Yoshimura, Yutaka ; et al.	2003-04-10
Computer forming logical partitions App 20020112102 - Tarui, Toshiaki ; et al.	2002-08-15
Apparatus and method for dynamically allocating computer resources based on service contract with user App 20020059427 - Tamaki, Yoshiko ; et al.	2002-05-16
Shared memory multiprocessor performing cache coherence control and node controller therefor App 20010005873 - Yasuda, Yoshiko ; et al.	2001-06-28
Automatic logic designing method and system Grant 5,504,690 - Kageyama , et al. April 2, 1	1996-04-02

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