| Patent | Date |
|---|
Accelerator Architecture On A Programmable Platform
App 20190065188 - Shippy; David ; et al. | 2019-02-28 |
Accelerator architecture on a programmable platform
Grant 10,095,647 - Shippy , et al. October 9, 2 | 2018-10-09 |
Accelerator Architecture On A Programmable Platform
App 20150347338 - Shippy; David ; et al. | 2015-12-03 |
Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates
Grant 8,082,423 - Abernathy , et al. December 20, 2 | 2011-12-20 |
Method and apparatus for delaying a load miss flush until issuing the dependent instruction
Grant 7,953,960 - Feiste , et al. May 31, 2 | 2011-05-31 |
Time-of-life counter for handling instruction flushes from a queue
Grant 7,913,070 - Abernathy , et al. March 22, 2 | 2011-03-22 |
Handling data cache misses out-of-order for asynchronous pipelines
Grant 7,900,024 - Abernathy , et al. March 1, 2 | 2011-03-01 |
Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor
Grant 7,831,808 - Abernathy , et al. November 9, 2 | 2010-11-09 |
Load address dependency mechanism system and method in a high frequency, low power processor system
Grant 7,769,985 - Barrick , et al. August 3, 2 | 2010-08-03 |
Dynamic power management in a processor design
Grant 7,681,056 - Abernathy , et al. March 16, 2 | 2010-03-16 |
Architected register file system utilizes status and control registers to control read/write operations between threads
Grant 7,596,682 - Shippy September 29, 2 | 2009-09-29 |
Handling Data Cache Misses Out-of-Order for Asynchronous Pipelines
App 20090043995 - Abernathy; Christopher M. ; et al. | 2009-02-12 |
Time-Of-Life Counter For Handling Instruction Flushes From A Queue
App 20090043997 - Abernathy; Christopher Michael ; et al. | 2009-02-12 |
Time-of-life counter design for handling instruction flushes from a queue
Grant 7,490,224 - Abernathy , et al. February 10, 2 | 2009-02-10 |
Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
Grant 7,461,239 - Abernathy , et al. December 2, 2 | 2008-12-02 |
Dynamic Power Management in a Processor Design
App 20080229078 - Abernathy; Christopher Michael ; et al. | 2008-09-18 |
Dynamic power management in a processor design
Grant 7,401,242 - Abernathy , et al. July 15, 2 | 2008-07-15 |
Queue Design System Supporting Dependency Checking And Issue For Simd Instructions Within A General Purpose Processor
App 20080168261 - Abernathy; Christopher Michael ; et al. | 2008-07-10 |
High Frequency Stall Design
App 20080148021 - DeMent; Jonathan James ; et al. | 2008-06-19 |
Load Address Dependency Mechanism System And Method In A High Frequency, Low Power Processor System
App 20080141014 - Barrick; Brian David ; et al. | 2008-06-12 |
System and method for high frequency stall design
Grant 7,370,176 - DeMent , et al. May 6, 2 | 2008-05-06 |
Load address dependency mechanism system and method in a high frequency, low power processor system
Grant 7,363,468 - Barrick , et al. April 22, 2 | 2008-04-22 |
Method and apparatus for issuing instructions from an issue queue in an information handling system
Grant 7,350,056 - Abernathy , et al. March 25, 2 | 2008-03-25 |
Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor
Grant 7,328,330 - Abernathy , et al. February 5, 2 | 2008-02-05 |
Fine grained multi-thread dispatch block mechanism
Grant 7,313,673 - Abernathy , et al. December 25, 2 | 2007-12-25 |
Method and apparatus for distributing flush instructions
App 20070198814 - Abernathy; Christopher Michael ; et al. | 2007-08-23 |
Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
App 20070198812 - Abernathy; Christopher Michael ; et al. | 2007-08-23 |
Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
App 20070180221 - Abernathy; Christopher M. ; et al. | 2007-08-02 |
System and method for dynamically selecting storage instruction performance scheme
App 20070118726 - Abernathy; Christopher Michael ; et al. | 2007-05-24 |
Method for dynamically choosing between varying processor error resolutions
App 20070088989 - Abernathy; Christopher M. ; et al. | 2007-04-19 |
Method and apparatus for delaying a load miss flush until issuing the dependent instruction
App 20070088935 - Feiste; Kurt Alan ; et al. | 2007-04-19 |
System and method for time-of-life counter design for handling instruction flushes from a queue
App 20070083742 - Abernathy; Christopher Michael ; et al. | 2007-04-12 |
Queue design supporting dependency checking and issue for simd instructions within a general purpose processor
App 20070083734 - Abernathy; Christopher Michael ; et al. | 2007-04-12 |
Method and apparatus for issuing instructions from an issue queue in an information handling system
App 20070074005 - Abernathy; Christopher Michael ; et al. | 2007-03-29 |
System and method for dynamic power management in a processor design
App 20070074059 - Abernathy; Christopher Michael ; et al. | 2007-03-29 |
System and method for high frequency stall design
App 20070043931 - DeMent; Jonathan James ; et al. | 2007-02-22 |
Fine grained multi-thread dispatch block mechanism
App 20060288192 - Abernathy; Christopher Michael ; et al. | 2006-12-21 |
Software-controlled cache set management
Grant 7,120,748 - Day , et al. October 10, 2 | 2006-10-10 |
System and method for handling multi-cycle non-pipelined instruction sequencing
App 20060224864 - DeMent; Jonathan James ; et al. | 2006-10-05 |
Software-controlled cache set management with software-generated class identifiers
Grant 7,114,035 - Day , et al. September 26, 2 | 2006-09-26 |
Memory management for real-time applications
Grant 7,103,748 - Day , et al. September 5, 2 | 2006-09-05 |
Load address dependency mechanism system and method in a high frequency, low power processor system
App 20060106987 - Barrick; Brian David ; et al. | 2006-05-18 |
Memory management in multiprocessor system
Grant 6,981,072 - Day , et al. December 27, 2 | 2005-12-27 |
Architected register file extension in a multi-thread processor
App 20050228975 - Shippy, David | 2005-10-13 |
Software-controlled cache set management with software-generated class identifiers
App 20050055505 - Day, Michael Norman ; et al. | 2005-03-10 |
Software-controlled cache set management
App 20050055507 - Day, Michael Norman ; et al. | 2005-03-10 |
Memory management in multiprocessor system
App 20040249995 - Day, Michael Norman ; et al. | 2004-12-09 |
On-chip data transfer in multi-processor system
Grant 6,820,143 - Day , et al. November 16, 2 | 2004-11-16 |
On-chip data transfer in multi-processor system
App 20040117520 - Day, Michael Norman ; et al. | 2004-06-17 |
Memory management for real-time applications
App 20040117592 - Day, Michael Norman ; et al. | 2004-06-17 |
Multithreading recycle and dispatch mechanism
App 20040111594 - Feiste, Kurt Alan ; et al. | 2004-06-10 |
Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units
Grant 6,061,780 - Shippy , et al. May 9, 2 | 2000-05-09 |
Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache
Grant 5,822,755 - Shippy October 13, 1 | 1998-10-13 |
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