Shioyama; Yoshiyuki

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shioyama; Yoshiyuki.The latest application filed is for "simulation apparatus, simulation method and non-transitory computer readable recording medium".

Company Profile

0.12.8

Shioyama; Yoshiyuki - Yokkaichi N/A JP
SHIOYAMA; Yoshiyuki - Yokkaichi-Shi JP
Shioyama; Yoshiyuki - Kanagawa JP
Shioyama; Yoshiyuki - Kawasaki JP
Shioyama; Yoshiyuki - Yokohama JP
Shioyama; Yoshiyuki - Kawasaki-shi JP
Shioyama, Yoshiyuki - Yokohama-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Simulation apparatus, simulation method and non-transitory computer readable recording medium Grant 9,183,673 - Omodaka , et al. November 10, 2	2015-11-10
Defect analyzing method and defect analyzing apparatus Grant 8,965,551 - Shioyama February 24, 2	2015-02-24
Simulation Apparatus, Simulation Method And Non-transitory Computer Readable Recording Medium App 20140063010 - OMODAKA; Ai ; et al.	2014-03-06
Defect Analyzing Method And Defect Analyzing Apparatus App 20120046778 - SHIOYAMA; Yoshiyuki	2012-02-23
Method for analyzing fail bit maps of waters and apparatus therefor Grant 7,405,088 - Matsushita , et al. July 29, 2	2008-07-29
Solid-state image pickup apparatus Grant 7,224,003 - Nakamura , et al. May 29, 2	2007-05-29
Design system of alignment marks for semiconductor manufacture Grant 7,100,146 - Sato , et al. August 29, 2	2006-08-29
Solid-state image pickup apparatus App 20060163684 - Nakamura; Nobuo ; et al.	2006-07-27
Failure detection system, failure detection method, and computer program product Grant 7,043,384 - Matsushita , et al. May 9, 2	2006-05-09
Solid-state image pickup apparatus Grant 7,042,061 - Nakamura , et al. May 9, 2	2006-05-09
Failure detection system, failure detection method, and computer program product App 20050102591 - Matsushita, Hiroshi ; et al.	2005-05-12
Method for analyzing fail bit maps of wafers and apparatus therefor App 20040255198 - Matsushita, Hiroshi ; et al.	2004-12-16
Design system of alignment marks for semiconductor manufacture App 20040207856 - Sato, Takashi ; et al.	2004-10-21
Solid-state image pickup apparatus App 20040108502 - Nakamura, Nobuo ; et al.	2004-06-10
Solid-state image pickup apparatus Grant 6,690,423 - Nakamura , et al. February 10, 2	2004-02-10
Solid state imaging device with four-phase charge-coupled device and method of manufacturing the same Grant 6,335,220 - Shioyama , et al. January 1, 2	2002-01-01
Apparatus for conveying and processing a wafer in a physically contact-free state Grant 5,747,780 - Shioyama , et al. May 5, 1	1998-05-05

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