Shinomiya; Noriko

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shinomiya; Noriko.The latest application filed is for "semiconductor integrated circuit, and method and apparatus for designing wiring pattern of semiconductor integrated circuit".

Company Profile

0.7.6

Shinomiya; Noriko - Osaka JP
Shinomiya; Noriko - Ibaraki JP
Shinomiya; Noriko - Ibaraki-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor integrated circuit apparatus with low wiring resistance Grant 8,024,689 - Shinomiya , et al. September 20, 2	2011-09-20
Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media Grant 7,441,214 - Shinomiya October 21, 2	2008-10-21
Semiconductor integrated circuit, and method and apparatus for designing wiring pattern of semiconductor integrated circuit App 20070272949 - Shinomiya; Noriko ; et al.	2007-11-29
Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media Grant 7,139,989 - Shinomiya November 21, 2	2006-11-21
Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media App 20060150134 - Shinomiya; Noriko	2006-07-06
Layout symmetry constraint checking method and layout symmetry constraint checking apparatus App 20060038201 - Shinomiya; Noriko ; et al.	2006-02-23
Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media App 20040103381 - Shinomiya, Noriko	2004-05-27
Semiconductor integrated circuit device, design method for the same and computer-readable recording where medium I/O cell library is recorded Grant 6,560,759 - Shinomiya May 6, 2	2003-05-06
Method and apparatus for designing LSI layout, cell library for designing LSI layout and semiconductor integrated circuit Grant 6,336,207 - Shinomiya , et al. January 1, 2	2002-01-01
Method And Apparatus For Designing Lsi Layout, Cell Library For Designing Lsi Layout And Semiconductor Integrated Circuit App 20010049815 - SHINOMIYA, NORIKO ; et al.	2001-12-06
Semiconductor integrated circuit device, design method for the same and computer-readable recording medium where I/O cell library is recorded App 20010015447 - Shinomiya, Noriko	2001-08-23
Compaction method, compaction apparatus, routing method and routing apparatus Grant 5,943,486 - Fukui , et al. August 24, 1	1999-08-24
Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones Grant 5,852,562 - Shinomiya , et al. December 22, 1	1998-12-22

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