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name:-0.017642974853516
name:-0.019802093505859
name:-0.0078749656677246
SHIMABUKURO; Seiji Patent Filings

SHIMABUKURO; Seiji

Patent Applications and Registrations

Patent applications and USPTO patent grants for SHIMABUKURO; Seiji.The latest application filed is for "three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same".

Company Profile
7.20.20
  • SHIMABUKURO; Seiji - Yokkaichi JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Three-dimensional Memory Device Containing Bridges For Enhanced Structural Support And Methods Of Forming The Same
App 20220254733 - MIZUNO; Genta ;   et al.
2022-08-11
Three-dimensional Memory Device With Backside Support Pillar Structures And Methods Of Forming The Same
App 20220223614 - TAKUMA; Shunsuke ;   et al.
2022-07-14
Method And Apparatus For Depositing A Multi-sector Film On Backside Of A Semiconductor Wafer
App 20210388500 - SHIMABUKURO; Seiji ;   et al.
2021-12-16
Method And Apparatus For Depositing A Multi-sector Film On Backside Of A Semiconductor Wafer
App 20210388502 - SHIMABUKURO; Seiji ;   et al.
2021-12-16
Three-dimensional Memory Device Containing Auxiliary Support Pillar Structures And Method Of Making The Same
App 20210358936 - TAKUMA; Shunsuke ;   et al.
2021-11-18
Contact via structure including a barrier metal disc for low resistance contact and methods of making the same
Grant 10,818,545 - Shimabukuro , et al. October 27, 2
2020-10-27
Three-dimensional memory device containing offset column stairs and method of making the same
Grant 10,546,870 - Shimabukuro , et al. Ja
2020-01-28
Contact Via Structure Including A Barrier Metal Disc For Low Resistance Contact And Methods Of Making The Same
App 20200006131 - Shimabukuro; Seiji ;   et al.
2020-01-02
Method for forming hydrogen-passivated semiconductor channels in a three-dimensional memory device
Grant 10,468,413 - Takuma , et al. No
2019-11-05
Method For Forming Hydrogen-passivated Semiconductor Channels In A Three-dimensional Memory Device
App 20190312035 - Takuma; Shunsuke ;   et al.
2019-10-10
Three-dimensional Memory Device Containing Offset Column Stairs And Method Of Making The Same
App 20190221574 - SHIMABUKURO; Seiji ;   et al.
2019-07-18
Three-dimensional resistive random access memory device containing selectively grown amorphous silicon-containing barrier and method of making the same
Grant 10,354,859 - Kamiya , et al. July 16, 2
2019-07-16
Multi-tier three-dimensional memory device with stress compensation structures and method of making thereof
Grant 10,355,012 - Shimabukuro , et al. July 16, 2
2019-07-16
Multi-tier Three-dimensional Memory Device With Stress Compensation Structures And Method Of Making Thereof
App 20180374865 - SHIMABUKURO; Seiji ;   et al.
2018-12-27
Three-dimensional Memory Device Containing Support Pillars Underneath A Retro-stepped Dielectric Material And Method Of Making Thereof
App 20180342531 - Susuki; Hiromasa ;   et al.
2018-11-29
Three-dimensional memory device containing support pillars underneath a retro-stepped dielectric material and method of making thereof
Grant 10,141,331 - Susuki , et al. Nov
2018-11-27
Resistive RAM including air gaps between word lines and between vertical bit lines
Grant 9,911,790 - Shimabukuro , et al. March 6, 2
2018-03-06
Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches
Grant 9,887,240 - Shimabukuro , et al. February 6, 2
2018-02-06
Three dimensional memory device having well contact pillar and method of making thereof
Grant 9,768,186 - Shimabukuro , et al. September 19, 2
2017-09-19
Set of stepped surfaces formation for a multilevel interconnect structure
Grant 9,728,499 - Shimabukuro , et al. August 8, 2
2017-08-08
Vertical thin film transistor selection devices and methods of fabrication
Grant 9,711,650 - Shimabukuro July 18, 2
2017-07-18
Method Of Fabricating Memory Array Having Divided Apart Bit Lines And Partially Divided Bit Line Selector Switches
App 20170154925 - Shimabukuro; Seiji ;   et al.
2017-06-01
Method of operating memory array having divided apart bit lines and partially divided bit line selector switches
Grant 9,608,043 - Shimabukuro , et al. March 28, 2
2017-03-28
Method of reducing control gate electrode curvature in three-dimensional memory devices
Grant 9,589,839 - Ikawa , et al. March 7, 2
2017-03-07
Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings
Grant 9,576,967 - Kimura , et al. February 21, 2
2017-02-21
Three Dimensional Memory Device Having Well Contact Pillar And Method Of Making Thereof
App 20160329341 - Shimabukuro; Seiji ;   et al.
2016-11-10
Vertical Thin Film Transistor Selection Devices And Methods Of Fabrication
App 20160308064 - Shimabukuro; Seiji
2016-10-20
Method Of Operating Memory Array Having Divided Apart Bit Lines And Partially Divided Bit Line Selector Switches
App 20160268340 - Shimabukuro; Seiji ;   et al.
2016-09-15
Three-dimensional memory structure employing air gap isolation
Grant 9,419,012 - Shimabukuro , et al. August 16, 2
2016-08-16
Three dimensional memory device having well contact pillar and method of making thereof
Grant 9,412,749 - Shimabukuro , et al. August 9, 2
2016-08-09
Vertical thin film transistor selection devices and methods of fabrication
Grant 9,379,246 - Shimabukuro June 28, 2
2016-06-28
Memory array having divided apart bit lines and partially divided bit line selector switches
Grant 9,356,074 - Shimabukuro , et al. May 31, 2
2016-05-31
Set Of Stepped Surfaces Formation For A Multilevel Interconnect Structure
App 20160148835 - SHIMABUKURO; Seiji ;   et al.
2016-05-26
Bottom Recess Process For An Outer Blocking Dielectric Layer Inside A Memory Opening
App 20160111439 - Tsutsumi; Masanori ;   et al.
2016-04-21
Bottom recess process for an outer blocking dielectric layer inside a memory opening
Grant 9,305,937 - Tsutsumi , et al. April 5, 2
2016-04-05
Floating gate ultrahigh density vertical NAND flash memory
Grant 9,159,739 - Makala , et al. October 13, 2
2015-10-13
Vertical Thin Film Transistor Selection Devices And Methods Of Fabrication
App 20150255619 - Shimabukuro; Seiji
2015-09-10
Floating Gate Ultrahigh Density Vertical Nand Flash Memory And Method Of Making Thereof
App 20140353738 - Makala; Raghuveer S. ;   et al.
2014-12-04
Selective Air Gap Isolation In Non-Volatile Memory
App 20130307044 - Kinoshita; Hiroyuki ;   et al.
2013-11-21

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