| Patent | Date |
|---|
Method and system of providing dynamic optimization information in a code interpretive runtime environment
Grant 6,412,107 - Cyran , et al. June 25, 2 | 2002-06-25 |
Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer
Grant 6,338,137 - Shiell , et al. January 8, 2 | 2002-01-08 |
Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
Grant 6,317,820 - Shiell , et al. November 13, 2 | 2001-11-13 |
Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability
Grant 6,216,219 - Cai , et al. April 10, 2 | 2001-04-10 |
Microprocessor system with block move circuit disposed between cache circuits
Grant 6,212,601 - Shiell April 3, 2 | 2001-04-03 |
Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding
Grant 6,209,114 - Wolf , et al. March 27, 2 | 2001-03-27 |
Prefetch circuity for prefetching variable size data
Grant 6,195,735 - Krueger , et al. February 27, 2 | 2001-02-27 |
Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal
Grant 6,173,368 - Krueger , et al. January 9, 2 | 2001-01-09 |
Microprocessor circuits, systems and methods for conditioning information prefetching based on resource burden
Grant 6,173,410 - Bondi , et al. January 9, 2 | 2001-01-09 |
Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy
Grant 6,170,053 - Anderson , et al. January 2, 2 | 2001-01-02 |
Method and apparatus for preemptive cache write-back
Grant 6,134,634 - Marshall, Jr. , et al. October 17, 2 | 2000-10-17 |
Combined branch prediction and cache prefetch in a microprocessor
Grant 6,119,222 - Shiell , et al. September 12, 2 | 2000-09-12 |
Dynamically loadable pattern history tables in a multi-task microprocessor
Grant 6,108,775 - Shiell , et al. August 22, 2 | 2000-08-22 |
Configurable expansion bus controller in a microprocessor-based system
Grant 6,085,269 - Chan , et al. July 4, 2 | 2000-07-04 |
High speed integrated circuit interconnection having proximally located active converter
Grant 6,064,254 - Vogley , et al. May 16, 2 | 2000-05-16 |
Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register
Grant 6,065,113 - Shiell , et al. May 16, 2 | 2000-05-16 |
Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure
Grant 6,049,672 - Shiell , et al. April 11, 2 | 2000-04-11 |
Emulation devices utilizing state machines
Grant 6,041,176 - Shiell March 21, 2 | 2000-03-21 |
Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache
Grant 6,038,645 - Nanda , et al. March 14, 2 | 2000-03-14 |
Microprocessor system with burstable, non-cacheable memory access support
Grant 6,032,225 - Shiell , et al. February 29, 2 | 2000-02-29 |
Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions
Grant 6,029,228 - Cai , et al. February 22, 2 | 2000-02-22 |
Microprocessor with circuits, systems, and methods for interrupt handling during virtual task operation
Grant 5,974,440 - Brooks , et al. October 26, 1 | 1999-10-26 |
Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes
Grant 5,961,632 - Shiell , et al. October 5, 1 | 1999-10-05 |
Microprocessor system with capability for asynchronous bus transactions
Grant 5,963,721 - Shiell , et al. October 5, 1 | 1999-10-05 |
Microprocessor with reduced microcode space requirements due to improved branch target microaddress circuits, systems, and methods
Grant 5,958,046 - Bondi , et al. September 28, 1 | 1999-09-28 |
Apparatus for caching system management memory in a computer having a system management mode employing address translation
Grant 5,954,812 - Shiell , et al. September 21, 1 | 1999-09-21 |
Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle
Grant 5,951,679 - Anderson , et al. September 14, 1 | 1999-09-14 |
Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer
Grant 5,953,512 - Cai , et al. September 14, 1 | 1999-09-14 |
Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes
Grant 5,950,012 - Shiell , et al. September 7, 1 | 1999-09-07 |
Multi-stream complex instruction set microprocessor
Grant 5,913,049 - Shiell , et al. June 15, 1 | 1999-06-15 |
Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods
Grant 5,911,057 - Shiell June 8, 1 | 1999-06-08 |
Microprocessor using combined actual and speculative branch history prediction
Grant 5,864,697 - Shiell January 26, 1 | 1999-01-26 |
Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return
Grant 5,850,543 - Shiell , et al. December 15, 1 | 1998-12-15 |
Microprocessor with circuits, systems, and methods for selectively bypassing external interrupts past the monitor program during virtual program operation
Grant 5,826,084 - Brooks , et al. October 20, 1 | 1998-10-20 |
Circuits, systems, and methods for reducing microprogram memory power for multiway branching
Grant 5,815,697 - Bosshart , et al. September 29, 1 | 1998-09-29 |
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